[xen staging] x86: Use 32-bit counter for TLB clock on debug builds

[patchbot@xxxxxxx]

commit c42bb919d5aa58dc28df66f792f5a6b319b0ad03
Author:     Alejandro Vallejo <alejandro.garciavallejo@xxxxxxx>
AuthorDate: Tue Jan 13 13:09:58 2026 +0100
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Tue Jan 13 15:47:02 2026 +0000

    x86: Use 32-bit counter for TLB clock on debug builds
    
    Debug builds traditionally ship with a 10-bit counter for the TLB
    clock. This forces global TLB shootdowns with high frequency, making
    debug builds unsuitable for any form of real time testing.
    
    Remove this quirk, unifying release and debug under a wide counter.
    
    Signed-off-by: Alejandro Vallejo <alejandro.garciavallejo@xxxxxxx>
    Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
 xen/arch/x86/flushtlb.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c
index 09e676c151..23721bb52c 100644
--- a/xen/arch/x86/flushtlb.c
+++ b/xen/arch/x86/flushtlb.c
@@ -19,13 +19,6 @@
 #include <asm/pv/domain.h>
 #include <asm/spec_ctrl.h>
 
-/* Debug builds: Wrap frequently to stress-test the wrap logic. */
-#ifdef NDEBUG
-#define WRAP_MASK (0xFFFFFFFFU)
-#else
-#define WRAP_MASK (0x000003FFU)
-#endif
-
 #ifndef CONFIG_PV
 # undef X86_CR4_PCIDE
 # define X86_CR4_PCIDE 0
@@ -55,7 +48,7 @@ static u32 pre_flush(void)
         /* Clock wrapped: someone else is leading a global TLB shootdown. */
         if ( unlikely(t1 == 0) )
             goto skip_clocktick;
-        t2 = (t + 1) & WRAP_MASK;
+        t2 = t + 1;
     }
     while ( unlikely((t = cmpxchg(&tlbflush_clock, t1, t2)) != t1) );
 
--
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