[xen staging] x86/pv: Address MISRA C:2012 Rule 4.1

[patchbot@xxxxxxx]

commit 6069a752cd904c7f72da67edb748c46845b7ea2f
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Fri Dec 12 19:31:46 2025 +0000
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Tue Dec 30 16:02:38 2025 +0000

    x86/pv: Address MISRA C:2012 Rule 4.1
    
    MISRA doesn't like mixing hexadecimal escape sequences with ASCII text.  Use
    the same workaround as in commit cd5048353725 ("xen: address MISRA C:2012 
Rule
    4.1").
    
    No functional change.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Reviewed-by: Nicola Vetrini <nicola.vetrini@xxxxxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/pv/emul-inv-op.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/pv/emul-inv-op.c b/xen/arch/x86/pv/emul-inv-op.c
index 314ebd01cb..346ac1124d 100644
--- a/xen/arch/x86/pv/emul-inv-op.c
+++ b/xen/arch/x86/pv/emul-inv-op.c
@@ -26,7 +26,7 @@ static int emulate_forced_invalid_op(struct cpu_user_regs 
*regs)
         pv_inject_page_fault(0, eip + sizeof(sig) - rc);
         return EXCRET_fault_fixed;
     }
-    if ( memcmp(sig, "\xf\xbxen", sizeof(sig)) )
+    if ( memcmp(sig, "\xf\xb" "xen", sizeof(sig)) )
         return 0;
     eip += sizeof(sig);
 
--
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