[xen staging-4.19] x86/mce: Adjustments to intel_init_ppin()

[patchbot@xxxxxxx]

commit 880d61a783be958edcec8864920c549719292274
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Wed Sep 3 14:06:20 2025 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Wed Sep 3 14:06:20 2025 +0200

    x86/mce: Adjustments to intel_init_ppin()
    
    There's no family check gating intel_init_ppin(), making it incorrect to
    use on non Fam6 CPUs.
    
    Emerald Rapids is the final CPU to have PPIN but lack the architectural
    enumeration, so include it too.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
    master commit: 49e6eb744eba01f5d4b4cfce49154c0802d4f5c6
    master date: 2025-08-25 14:04:41 +0100
---
 xen/arch/x86/cpu/mcheck/mce_intel.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c 
b/xen/arch/x86/cpu/mcheck/mce_intel.c
index dd812f4b8a..76d6202809 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -10,6 +10,7 @@
 #include <xen/cpu.h>
 #include <asm/processor.h>
 #include <public/sysctl.h>
+#include <asm/intel-family.h>
 #include <asm/system.h>
 #include <asm/msr.h>
 #include <asm/p2m.h>
@@ -859,7 +860,7 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
      * other purposes.  Despite the late addition of a CPUID bit (rendering
      * the MSR architectural), keep using the same detection logic there.
      */
-    switch ( c->x86_model )
+    switch ( c->x86 == 6 ? c->x86_model : 0 )
     {
         uint64_t val;
 
@@ -870,16 +871,17 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
             return;
         }
         fallthrough;
-    case 0x3e: /* IvyBridge X */
-    case 0x3f: /* Haswell X */
-    case 0x4f: /* Broadwell X */
-    case 0x55: /* Skylake X */
-    case 0x56: /* Broadwell Xeon D */
-    case 0x57: /* Knights Landing */
-    case 0x6a: /* Icelake X */
-    case 0x6c: /* Icelake D */
-    case 0x85: /* Knights Mill */
-    case 0x8f: /* Sapphire Rapids X */
+    case INTEL_FAM6_IVYBRIDGE_X:
+    case INTEL_FAM6_HASWELL_X:
+    case INTEL_FAM6_BROADWELL_X:
+    case INTEL_FAM6_BROADWELL_D:
+    case INTEL_FAM6_SKYLAKE_X:
+    case INTEL_FAM6_XEON_PHI_KNL:
+    case INTEL_FAM6_XEON_PHI_KNM:
+    case INTEL_FAM6_ICELAKE_X:
+    case INTEL_FAM6_ICELAKE_D:
+    case INTEL_FAM6_SAPPHIRERAPIDS_X:
+    case INTEL_FAM6_EMERALDRAPIDS_X:
 
         if ( (c != &boot_cpu_data && !ppin_msr) ||
              rdmsr_safe(MSR_PPIN_CTL, val) )
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.19