|
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [xen staging] x86/msr: Split out fsgsbase.h
commit 9e544443716ead4cc09a09fe00ae74620ea2d54b
Author: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Thu Aug 14 14:32:03 2025 +0100
Commit: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Tue Aug 19 19:52:48 2025 +0100
x86/msr: Split out fsgsbase.h
It is a large and complex API, but only a handful of translation units need
access.
No functional change.
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
---
xen/arch/x86/domain.c | 1 +
xen/arch/x86/hvm/vmx/vmx.c | 1 +
xen/arch/x86/include/asm/fsgsbase.h | 114 ++++++++++++++++++++++++++++++++++++
xen/arch/x86/include/asm/msr.h | 105 ---------------------------------
xen/arch/x86/pv/domain.c | 1 +
xen/arch/x86/pv/emul-priv-op.c | 1 +
xen/arch/x86/pv/misc-hypercalls.c | 1 +
xen/arch/x86/traps.c | 1 +
8 files changed, 120 insertions(+), 105 deletions(-)
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index dbf2ff14f5..cd56f5821a 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -44,6 +44,7 @@
#include <asm/cpuidle.h>
#include <asm/debugreg.h>
#include <asm/desc.h>
+#include <asm/fsgsbase.h>
#include <asm/guest-msr.h>
#include <asm/hvm/hvm.h>
#include <asm/hvm/nestedhvm.h>
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 4934449577..5439f950dc 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -22,6 +22,7 @@
#include <asm/current.h>
#include <asm/debugreg.h>
#include <asm/event.h>
+#include <asm/fsgsbase.h>
#include <asm/gdbsx.h>
#include <asm/guest-msr.h>
#include <asm/hvm/emulate.h>
diff --git a/xen/arch/x86/include/asm/fsgsbase.h
b/xen/arch/x86/include/asm/fsgsbase.h
new file mode 100644
index 0000000000..03e6a85d31
--- /dev/null
+++ b/xen/arch/x86/include/asm/fsgsbase.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef X86_FSGSBASE_H
+#define X86_FSGSBASE_H
+
+#include <asm/msr.h>
+#include <asm/processor.h>
+#include <asm/x86-defns.h>
+
+/*
+ * On hardware supporting FSGSBASE, the value loaded into hardware is the
+ * guest kernel's choice for 64bit PV guests (Xen's choice for Idle, HVM and
+ * 32bit PV).
+ *
+ * Therefore, the {RD,WR}{FS,GS}BASE instructions are only safe to use if
+ * %cr4.fsgsbase is set.
+ */
+static inline unsigned long __rdfsbase(void)
+{
+ unsigned long base;
+
+ asm volatile ( "rdfsbase %0" : "=r" (base) );
+
+ return base;
+}
+
+static inline unsigned long __rdgsbase(void)
+{
+ unsigned long base;
+
+ asm volatile ( "rdgsbase %0" : "=r" (base) );
+
+ return base;
+}
+
+static inline void __wrfsbase(unsigned long base)
+{
+ asm volatile ( "wrfsbase %0" :: "r" (base) );
+}
+
+static inline void __wrgsbase(unsigned long base)
+{
+ asm volatile ( "wrgsbase %0" :: "r" (base) );
+}
+
+static inline unsigned long read_fs_base(void)
+{
+ unsigned long base;
+
+ if ( read_cr4() & X86_CR4_FSGSBASE )
+ return __rdfsbase();
+
+ rdmsrl(MSR_FS_BASE, base);
+
+ return base;
+}
+
+static inline unsigned long read_gs_base(void)
+{
+ unsigned long base;
+
+ if ( read_cr4() & X86_CR4_FSGSBASE )
+ return __rdgsbase();
+
+ rdmsrl(MSR_GS_BASE, base);
+
+ return base;
+}
+
+static inline unsigned long read_gs_shadow(void)
+{
+ unsigned long base;
+
+ if ( read_cr4() & X86_CR4_FSGSBASE )
+ {
+ asm volatile ( "swapgs" );
+ base = __rdgsbase();
+ asm volatile ( "swapgs" );
+ }
+ else
+ rdmsrl(MSR_SHADOW_GS_BASE, base);
+
+ return base;
+}
+
+static inline void write_fs_base(unsigned long base)
+{
+ if ( read_cr4() & X86_CR4_FSGSBASE )
+ __wrfsbase(base);
+ else
+ wrmsrl(MSR_FS_BASE, base);
+}
+
+static inline void write_gs_base(unsigned long base)
+{
+ if ( read_cr4() & X86_CR4_FSGSBASE )
+ __wrgsbase(base);
+ else
+ wrmsrl(MSR_GS_BASE, base);
+}
+
+static inline void write_gs_shadow(unsigned long base)
+{
+ if ( read_cr4() & X86_CR4_FSGSBASE )
+ {
+ asm volatile ( "swapgs\n\t"
+ "wrgsbase %0\n\t"
+ "swapgs"
+ :: "r" (base) );
+ }
+ else
+ wrmsrl(MSR_SHADOW_GS_BASE, base);
+}
+
+#endif /* X86_FSGSBASE_H */
diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index 06afdb460a..9d1cb4e6ee 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -142,111 +142,6 @@ static inline uint64_t rdtsc_ordered(void)
: "=a" (low), "=d" (high) \
: "c" (counter))
-/*
- * On hardware supporting FSGSBASE, the value loaded into hardware is the
- * guest kernel's choice for 64bit PV guests (Xen's choice for Idle, HVM and
- * 32bit PV).
- *
- * Therefore, the {RD,WR}{FS,GS}BASE instructions are only safe to use if
- * %cr4.fsgsbase is set.
- */
-static inline unsigned long __rdfsbase(void)
-{
- unsigned long base;
-
- asm volatile ( "rdfsbase %0" : "=r" (base) );
-
- return base;
-}
-
-static inline unsigned long __rdgsbase(void)
-{
- unsigned long base;
-
- asm volatile ( "rdgsbase %0" : "=r" (base) );
-
- return base;
-}
-
-static inline void __wrfsbase(unsigned long base)
-{
- asm volatile ( "wrfsbase %0" :: "r" (base) );
-}
-
-static inline void __wrgsbase(unsigned long base)
-{
- asm volatile ( "wrgsbase %0" :: "r" (base) );
-}
-
-static inline unsigned long read_fs_base(void)
-{
- unsigned long base;
-
- if ( read_cr4() & X86_CR4_FSGSBASE )
- return __rdfsbase();
-
- rdmsrl(MSR_FS_BASE, base);
-
- return base;
-}
-
-static inline unsigned long read_gs_base(void)
-{
- unsigned long base;
-
- if ( read_cr4() & X86_CR4_FSGSBASE )
- return __rdgsbase();
-
- rdmsrl(MSR_GS_BASE, base);
-
- return base;
-}
-
-static inline unsigned long read_gs_shadow(void)
-{
- unsigned long base;
-
- if ( read_cr4() & X86_CR4_FSGSBASE )
- {
- asm volatile ( "swapgs" );
- base = __rdgsbase();
- asm volatile ( "swapgs" );
- }
- else
- rdmsrl(MSR_SHADOW_GS_BASE, base);
-
- return base;
-}
-
-static inline void write_fs_base(unsigned long base)
-{
- if ( read_cr4() & X86_CR4_FSGSBASE )
- __wrfsbase(base);
- else
- wrmsrl(MSR_FS_BASE, base);
-}
-
-static inline void write_gs_base(unsigned long base)
-{
- if ( read_cr4() & X86_CR4_FSGSBASE )
- __wrgsbase(base);
- else
- wrmsrl(MSR_GS_BASE, base);
-}
-
-static inline void write_gs_shadow(unsigned long base)
-{
- if ( read_cr4() & X86_CR4_FSGSBASE )
- {
- asm volatile ( "swapgs\n\t"
- "wrgsbase %0\n\t"
- "swapgs"
- :: "r" (base) );
- }
- else
- wrmsrl(MSR_SHADOW_GS_BASE, base);
-}
-
DECLARE_PER_CPU(uint64_t, efer);
static inline uint64_t read_efer(void)
{
diff --git a/xen/arch/x86/pv/domain.c b/xen/arch/x86/pv/domain.c
index 9334da1dab..9c4785c187 100644
--- a/xen/arch/x86/pv/domain.c
+++ b/xen/arch/x86/pv/domain.c
@@ -12,6 +12,7 @@
#include <asm/cpu-policy.h>
#include <asm/cpufeature.h>
+#include <asm/fsgsbase.h>
#include <asm/invpcid.h>
#include <asm/spec_ctrl.h>
#include <asm/pv/domain.h>
diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index f3f012f8fb..9f8600f43a 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -16,6 +16,7 @@
#include <asm/amd.h>
#include <asm/debugreg.h>
#include <asm/endbr.h>
+#include <asm/fsgsbase.h>
#include <asm/hpet.h>
#include <asm/mc146818rtc.h>
#include <asm/pv/domain.h>
diff --git a/xen/arch/x86/pv/misc-hypercalls.c
b/xen/arch/x86/pv/misc-hypercalls.c
index 17030d800d..7a37f16bf0 100644
--- a/xen/arch/x86/pv/misc-hypercalls.c
+++ b/xen/arch/x86/pv/misc-hypercalls.c
@@ -10,6 +10,7 @@
#include <xen/hypercall.h>
#include <asm/debugreg.h>
+#include <asm/fsgsbase.h>
long do_set_debugreg(int reg, unsigned long value)
{
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 270b93ed62..0c5393cb21 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -33,6 +33,7 @@
#include <asm/debugreg.h>
#include <asm/desc.h>
#include <asm/flushtlb.h>
+#include <asm/fsgsbase.h>
#include <asm/gdbsx.h>
#include <asm/i387.h>
#include <asm/io.h>
--
generated by git-patchbot for /home/xen/git/xen.git#staging
|
 |
Lists.xenproject.org is hosted with RackSpace, monitoring our |