[xen staging] x86: suppress ERMS for internal use when MISC_ENABLE.FAST_STRING is clear

[patchbot@xxxxxxx]

commit 5cbaa5d92e5019797d598f6286c7b9cb4a4adc1d
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Wed Jul 23 15:16:38 2025 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Wed Jul 23 15:16:38 2025 +0200

    x86: suppress ERMS for internal use when MISC_ENABLE.FAST_STRING is clear
    
    Before we start actually adjusting behavior when ERMS is available,
    follow Linux commit 161ec53c702c ("x86, mem, intel: Initialize Enhanced
    REP MOVSB/STOSB") and zap the CPUID-derived feature flag when the MSR
    bit is clear.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Reviewed-by: Jason Andryuk <jason.andryuk@xxxxxxx>
---
 xen/arch/x86/cpu-policy.c            | 13 +++++++++++++
 xen/arch/x86/cpu/intel.c             | 10 ++++++++++
 xen/arch/x86/include/asm/msr-index.h |  1 +
 3 files changed, 24 insertions(+)

diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
index 5ee8ce1ef7..42dccdce52 100644
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -501,6 +501,12 @@ static void __init 
guest_common_max_feature_adjustments(uint32_t *fs)
      */
     __set_bit(X86_FEATURE_HTT, fs);
     __set_bit(X86_FEATURE_CMP_LEGACY, fs);
+
+    /*
+     * ERMS is a performance hint.  A VM which previously saw ERMS will
+     * function correctly when migrated here, even if ERMS isn't available.
+     */
+    __set_bit(X86_FEATURE_ERMS, fs);
 }
 
 static void __init guest_common_default_feature_adjustments(uint32_t *fs)
@@ -588,6 +594,13 @@ static void __init 
guest_common_default_feature_adjustments(uint32_t *fs)
 
     if ( !cpu_has_cmp_legacy )
         __clear_bit(X86_FEATURE_CMP_LEGACY, fs);
+
+    /*
+     * ERMS is a performance hint, so is set unconditionally in the max
+     * policy.  However, guests should default to the host setting.
+     */
+    if ( !host_cpu_policy.feat.erms )
+        __clear_bit(X86_FEATURE_ERMS, fs);
 }
 
 static void __init guest_common_feature_adjustments(uint32_t *fs)
diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index faace882f1..29144ffe37 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -363,8 +363,18 @@ static void cf_check early_init_intel(struct cpuinfo_x86 
*c)
                paddr_bits = 36;
 
        if (c == &boot_cpu_data) {
+               uint64_t misc_enable;
+
                check_memory_type_self_snoop_errata();
 
+               /*
+                * If fast string is not enabled in IA32_MISC_ENABLE for any 
reason,
+                * clear the enhanced fast string CPU capability.
+                */
+               rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+               if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING))
+                       setup_clear_cpu_cap(X86_FEATURE_ERMS);
+
                intel_init_levelling();
        }
 
diff --git a/xen/arch/x86/include/asm/msr-index.h 
b/xen/arch/x86/include/asm/msr-index.h
index 6f2c3147e3..2e7e2aff9a 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -493,6 +493,7 @@
 #define MSR_IA32_THERM_INTERRUPT       0x0000019b
 #define MSR_IA32_THERM_STATUS          0x0000019c
 #define MSR_IA32_MISC_ENABLE           0x000001a0
+#define MSR_IA32_MISC_ENABLE_FAST_STRING  (1<<0)
 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL   (1<<7)
 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL  (1<<11)
 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
--
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