[xen staging-4.17] x86/cpu-policy: Infrastructure for CPUID leaf 0x80000021.ecx

[patchbot@xxxxxxx]

commit 77d74b02081d68f53b60e0383f7f9a86355c3e9a
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Tue Sep 10 19:55:15 2024 +0100
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Tue Jul 8 15:10:58 2025 +0100

    x86/cpu-policy: Infrastructure for CPUID leaf 0x80000021.ecx
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
    (cherry picked from commit 6e3c3cea091b3eacd85543af2ee7f33acab65a17)
---
 tools/libs/light/libxl_cpuid.c              | 1 +
 tools/misc/xen-cpuid.c                      | 5 +++++
 xen/arch/x86/cpu-policy.c                   | 1 -
 xen/arch/x86/cpu/common.c                   | 4 +++-
 xen/include/public/arch-x86/cpufeatureset.h | 2 ++
 xen/include/xen/lib/x86/cpu-policy.h        | 7 ++++++-
 xen/lib/x86/cpuid.c                         | 2 ++
 7 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c
index 5c66d094b2..493f615c9d 100644
--- a/tools/libs/light/libxl_cpuid.c
+++ b/tools/libs/light/libxl_cpuid.c
@@ -344,6 +344,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list 
*policy, const char* str)
         CPUID_ENTRY(0x00000007,  1, CPUID_REG_EDX),
         MSR_ENTRY(0x10a, CPUID_REG_EAX),
         MSR_ENTRY(0x10a, CPUID_REG_EDX),
+        CPUID_ENTRY(0x80000021, NA, CPUID_REG_ECX),
 #undef MSR_ENTRY
 #undef CPUID_ENTRY
     };
diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index b277b78b65..7704980b8a 100644
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -244,6 +244,10 @@ static const char *const str_m10Al[64] =
     [62] = "its-no",
 };
 
+static const char *const str_e21c[32] =
+{
+};
+
 static const struct {
     const char *name;
     const char *abbr;
@@ -268,6 +272,7 @@ static const struct {
     { "CPUID 0x00000007:1.edx",     "7d1", str_7d1 },
     { "MSR_ARCH_CAPS.lo",         "m10Al", str_m10Al },
     { "MSR_ARCH_CAPS.hi",         "m10Ah", str_m10Al + 32 },
+    { "CPUID 0x80000021.ecx",      "e21c", str_e21c },
 };
 
 #define COL_ALIGN "24"
diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
index 498fa4f995..b4d3fa8243 100644
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -341,7 +341,6 @@ static void recalculate_misc(struct cpu_policy *p)
         p->extd.raw[0x1f] = EMPTY_LEAF; /* SEV */
         p->extd.raw[0x20] = EMPTY_LEAF; /* Platform QoS */
         p->extd.raw[0x21].b = 0;
-        p->extd.raw[0x21].c = 0;
         p->extd.raw[0x21].d = 0;
         break;
     }
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 14a3a97806..5d648622fe 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -469,7 +469,9 @@ static void generic_identify(struct cpuinfo_x86 *c)
        if (c->extended_cpuid_level >= 0x80000008)
                c->x86_capability[FEATURESET_e8b] = cpuid_ebx(0x80000008);
        if (c->extended_cpuid_level >= 0x80000021)
-               c->x86_capability[FEATURESET_e21a] = cpuid_eax(0x80000021);
+               cpuid(0x80000021,
+                     &c->x86_capability[FEATURESET_e21a], &tmp,
+                     &c->x86_capability[FEATURESET_e21c], &tmp);
 
        /* Intel-defined flags: level 0x00000007 */
        if (c->cpuid_level >= 7) {
diff --git a/xen/include/public/arch-x86/cpufeatureset.h 
b/xen/include/public/arch-x86/cpufeatureset.h
index 99c4dc1ffd..03cd1419c5 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -337,6 +337,8 @@ XEN_CPUFEATURE(RFDS_CLEAR,         16*32+28) /*!A Register 
File(s) cleared by VE
 /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.edx, word 17 (express in 
terms of word 16) */
 XEN_CPUFEATURE(ITS_NO,             16*32+62) /*!A No Indirect Target Selection 
*/
 
+/* AMD-defined CPU features, CPUID level 0x80000021.ecx, word 18 */
+
 #endif /* XEN_CPUFEATURE */
 
 /* Clean up from a default include.  Close the enum (for C). */
diff --git a/xen/include/xen/lib/x86/cpu-policy.h 
b/xen/include/xen/lib/x86/cpu-policy.h
index ba29bfe9b4..7bb90edf83 100644
--- a/xen/include/xen/lib/x86/cpu-policy.h
+++ b/xen/include/xen/lib/x86/cpu-policy.h
@@ -22,6 +22,7 @@
 #define FEATURESET_7d1       15 /* 0x00000007:1.edx    */
 #define FEATURESET_m10Al     16 /* 0x0000010a.eax      */
 #define FEATURESET_m10Ah     17 /* 0x0000010a.edx      */
+#define FEATURESET_e21c      18 /* 0x80000021.ecx      */
 
 struct cpuid_leaf
 {
@@ -327,7 +328,11 @@ struct cpu_policy
             uint16_t ucode_size; /* Units of 16 bytes */
             uint8_t  rap_size;   /* Units of 8 entries */
             uint8_t  :8;
-            uint32_t /* c */:32, /* d */:32;
+            union {
+                uint32_t e21c;
+                struct { DECL_BITFIELD(e21c); };
+            };
+            uint32_t /* d */:32;
         };
     } extd;
 
diff --git a/xen/lib/x86/cpuid.c b/xen/lib/x86/cpuid.c
index 07e5501914..22fd162c9d 100644
--- a/xen/lib/x86/cpuid.c
+++ b/xen/lib/x86/cpuid.c
@@ -81,6 +81,7 @@ void x86_cpu_policy_to_featureset(
     fs[FEATURESET_7d1]       = p->feat._7d1;
     fs[FEATURESET_m10Al]     = p->arch_caps.lo;
     fs[FEATURESET_m10Ah]     = p->arch_caps.hi;
+    fs[FEATURESET_e21c]      = p->extd.e21c;
 }
 
 void x86_cpu_featureset_to_policy(
@@ -104,6 +105,7 @@ void x86_cpu_featureset_to_policy(
     p->feat._7d1             = fs[FEATURESET_7d1];
     p->arch_caps.lo          = fs[FEATURESET_m10Al];
     p->arch_caps.hi          = fs[FEATURESET_m10Ah];
+    p->extd.e21c             = fs[FEATURESET_e21c];
 }
 
 void x86_cpu_policy_recalc_synth(struct cpu_policy *p)
--
generated by git-patchbot for /home/xen/git/xen.git#staging-4.17