[xen staging] arm/vgic-v3: Fix GICD_ICPENDR read access in __vgic_v3_distr_common_mmio_read()

[patchbot@xxxxxxx]

commit 861e7862b8faf25129fb6df33c1cee333a34c404
Author:     Oleksandr Tyshchenko <Oleksandr_Tyshchenko@xxxxxxxx>
AuthorDate: Tue May 27 00:11:52 2025 +0000
Commit:     Michal Orzel <michal.orzel@xxxxxxx>
CommitDate: Wed May 28 11:39:00 2025 +0200

    arm/vgic-v3: Fix GICD_ICPENDR read access in 
__vgic_v3_distr_common_mmio_read()
    
    An attempt to read access the GICD_ICPENDR<n> register (where n > 0)
    which should be RAZ (as not supported) causes the guest data abort
    due to incorrect end offset (GICD_ICPENDR) in the case range.
    Fix that by using the proper end offset (GICD_ICPENDRN).
    
    Fixes: a2b83f95bfa ("xen/arm: vgic: Properly emulate the full register")
    Signed-off-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@xxxxxxxx>
    Reviewed-by: Michal Orzel <michal.orzel@xxxxxxx>
---
 xen/arch/arm/vgic-v3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index f20249f731..4369c55177 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -709,7 +709,7 @@ static int __vgic_v3_distr_common_mmio_read(const char 
*name, struct vcpu *v,
 
     /* Read the pending status of an IRQ via GICD/GICR is not supported */
     case VRANGE32(GICD_ISPENDR, GICD_ISPENDRN):
-    case VRANGE32(GICD_ICPENDR, GICD_ICPENDR):
+    case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN):
         goto read_as_zero;
 
     /* Read the active status of an IRQ via GICD/GICR is not supported */
--
generated by git-patchbot for /home/xen/git/xen.git#staging