[xen master] xen/riscv: make zbb as mandatory

[patchbot@xxxxxxx]

commit 4c91847903915aa99172d054e1add85e65afc264
Author:     Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
AuthorDate: Thu Mar 6 14:01:53 2025 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Thu Mar 6 14:01:53 2025 +0100

    xen/riscv: make zbb as mandatory
    
    According to riscv/booting.txt, it is expected that Zbb should be supported.
    
    Drop ANDN_INSN() in asm/cmpxchg.h as Zbb is mandatory now so `andn`
    instruction could be used directly.
    
    Signed-off-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/riscv/arch.mk               |  7 ++-----
 xen/arch/riscv/include/asm/cmpxchg.h | 15 +--------------
 2 files changed, 3 insertions(+), 19 deletions(-)

diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk
index 3034da76cb..236ea7c8a6 100644
--- a/xen/arch/riscv/arch.mk
+++ b/xen/arch/riscv/arch.mk
@@ -9,7 +9,7 @@ riscv-abi-$(CONFIG_RISCV_64) := -mabi=lp64
 riscv-march-$(CONFIG_RISCV_64) := rv64
 riscv-march-y += ima
 riscv-march-$(CONFIG_RISCV_ISA_C) += c
-riscv-march-y += _zicsr_zifencei
+riscv-march-y += _zicsr_zifencei_zbb
 
 riscv-generic-flags := $(riscv-abi-y) -march=$(subst 
$(space),,$(riscv-march-y))
 
@@ -25,13 +25,10 @@ $(eval $(1) := \
        $(call as-insn,$(CC) $(riscv-generic-flags)_$(1),$(value 
$(1)-insn),_$(1)))
 endef
 
-zbb-insn := "andn t0$(comma)t0$(comma)t0"
-$(call check-extension,zbb)
-
 zihintpause-insn := "pause"
 $(call check-extension,zihintpause)
 
-extensions := $(zbb) $(zihintpause)
+extensions := $(zihintpause)
 
 extensions := $(subst $(space),,$(extensions))
 
diff --git a/xen/arch/riscv/include/asm/cmpxchg.h 
b/xen/arch/riscv/include/asm/cmpxchg.h
index 662d3fd5d4..7d7c89b6fa 100644
--- a/xen/arch/riscv/include/asm/cmpxchg.h
+++ b/xen/arch/riscv/include/asm/cmpxchg.h
@@ -18,19 +18,6 @@
         : "r" (new) \
         : "memory" );
 
-/*
- * To not face an issue that gas doesn't understand ANDN instruction
- * it is encoded using .insn directive.
- */
-#ifdef __riscv_zbb
-#define ANDN_INSN(rd, rs1, rs2)                 \
-    ".insn r OP, 0x7, 0x20, " rd ", " rs1 ", " rs2 "\n"
-#else
-#define ANDN_INSN(rd, rs1, rs2)                 \
-    "not " rd ", " rs2 "\n"                     \
-    "and " rd ", " rs1 ", " rd "\n"
-#endif
-
 /*
  * For LR and SC, the A extension requires that the address held in rs1 be
  * naturally aligned to the size of the operand (i.e., eight-byte aligned
@@ -61,7 +48,7 @@
     \
     asm volatile ( \
         "0: lr.w" lr_sfx " %[old], %[ptr_]\n" \
-        ANDN_INSN("%[scratch]", "%[old]", "%[mask]") \
+        "   andn  %[scratch], %[old], %[mask]\n" \
         "   or   %[scratch], %[scratch], %z[new_]\n" \
         "   sc.w" sc_sfx " %[scratch], %[scratch], %[ptr_]\n" \
         "   bnez %[scratch], 0b\n" \
--
generated by git-patchbot for /home/xen/git/xen.git#master