[xen master] xen/x86: add CPPC feature flag for AMD processors

[patchbot@xxxxxxx]

commit 01bdc6d2d285738767991658754de123a3d07ff8
Author:     Penny Zheng <Penny.Zheng@xxxxxxx>
AuthorDate: Tue Feb 25 08:41:41 2025 +0100
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Tue Feb 25 08:41:41 2025 +0100

    xen/x86: add CPPC feature flag for AMD processors
    
    Add Collaborative Processor Performance Control feature flag for
    AMD processors.
    
    amd-cppc is the AMD CPU performance scaling driver that
    introduces a new CPU frequency control mechanism on modern AMD
    APU and CPU series.
    There are two types of hardware implementations: "Full MSR Support"
    and "Shared Memory Support".
    
    Right now, xen will only implement "Full MSR Support", and this new
    feature flag indicates whether processor has this feature or not.
    
    Signed-off-by: Penny Zheng <Penny.Zheng@xxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/include/asm/cpufeature.h       | 1 +
 xen/include/public/arch-x86/cpufeatureset.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/xen/arch/x86/include/asm/cpufeature.h 
b/xen/arch/x86/include/asm/cpufeature.h
index 3a06b6f297..6935703e71 100644
--- a/xen/arch/x86/include/asm/cpufeature.h
+++ b/xen/arch/x86/include/asm/cpufeature.h
@@ -170,6 +170,7 @@ static inline bool boot_cpu_has(unsigned int feat)
 #define cpu_has_amd_ssbd        boot_cpu_has(X86_FEATURE_AMD_SSBD)
 #define cpu_has_virt_ssbd       boot_cpu_has(X86_FEATURE_VIRT_SSBD)
 #define cpu_has_ssb_no          boot_cpu_has(X86_FEATURE_SSB_NO)
+#define cpu_has_cppc            boot_cpu_has(X86_FEATURE_CPPC)
 #define cpu_has_auto_ibrs       boot_cpu_has(X86_FEATURE_AUTO_IBRS)
 
 /* CPUID level 0x00000007:0.edx */
diff --git a/xen/include/public/arch-x86/cpufeatureset.h 
b/xen/include/public/arch-x86/cpufeatureset.h
index 16207e3817..cc6e984a88 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -265,6 +265,7 @@ XEN_CPUFEATURE(AMD_PPIN,      8*32+23) /*   Protected 
Processor Inventory Number
 XEN_CPUFEATURE(AMD_SSBD,      8*32+24) /*S  MSR_SPEC_CTRL.SSBD available */
 XEN_CPUFEATURE(VIRT_SSBD,     8*32+25) /*!  MSR_VIRT_SPEC_CTRL.SSBD */
 XEN_CPUFEATURE(SSB_NO,        8*32+26) /*A  Hardware not vulnerable to SSB */
+XEN_CPUFEATURE(CPPC,          8*32+27) /*   Collaborative Processor 
Performance Control */
 XEN_CPUFEATURE(PSFD,          8*32+28) /*S  MSR_SPEC_CTRL.PSFD */
 XEN_CPUFEATURE(BTC_NO,        8*32+29) /*A  Hardware not vulnerable to Branch 
Type Confusion */
 XEN_CPUFEATURE(IBPB_RET,      8*32+30) /*A  IBPB clears RSB/RAS too. */
--
generated by git-patchbot for /home/xen/git/xen.git#master