[xen staging] x86/MCE: guard access to Intel/AMD-specific MCA MSRs

[patchbot@xxxxxxx]

commit 71b5eccbddb4cb94e816ed8e911f3aa00f866e5b
Author:     Sergiy Kibrik <Sergiy_Kibrik@xxxxxxxx>
AuthorDate: Thu May 16 13:35:34 2024 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Thu May 16 13:35:34 2024 +0200

    x86/MCE: guard access to Intel/AMD-specific MCA MSRs
    
    Add build-time checks for newly introduced INTEL/AMD config options when
    calling vmce_{intel/amd}_{rdmsr/wrmsr}() routines.
    This way a platform-specific code can be omitted in vmce code, if this
    platform is disabled in config.
    
    Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@xxxxxxxx>
    Reviewed-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/cpu/mcheck/vmce.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c
index 353d4f19b2..4da6f4a3e4 100644
--- a/xen/arch/x86/cpu/mcheck/vmce.c
+++ b/xen/arch/x86/cpu/mcheck/vmce.c
@@ -138,16 +138,20 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t 
msr, uint64_t *val)
     default:
         switch ( boot_cpu_data.x86_vendor )
         {
+#ifdef CONFIG_INTEL
         case X86_VENDOR_CENTAUR:
         case X86_VENDOR_SHANGHAI:
         case X86_VENDOR_INTEL:
             ret = vmce_intel_rdmsr(v, msr, val);
             break;
+#endif
 
+#ifdef CONFIG_AMD
         case X86_VENDOR_AMD:
         case X86_VENDOR_HYGON:
             ret = vmce_amd_rdmsr(v, msr, val);
             break;
+#endif
 
         default:
             ret = 0;
@@ -271,14 +275,18 @@ static int bank_mce_wrmsr(struct vcpu *v, uint32_t msr, 
uint64_t val)
     default:
         switch ( boot_cpu_data.x86_vendor )
         {
+#ifdef CONFIG_INTEL
         case X86_VENDOR_INTEL:
             ret = vmce_intel_wrmsr(v, msr, val);
             break;
+#endif
 
+#ifdef CONFIG_AMD
         case X86_VENDOR_AMD:
         case X86_VENDOR_HYGON:
             ret = vmce_amd_wrmsr(v, msr, val);
             break;
+#endif
 
         default:
             ret = 0;
--
generated by git-patchbot for /home/xen/git/xen.git#staging