[xen master] ARM: GICv3 ITS: flush caches for newly allocated ITT

[patchbot@xxxxxxx]

commit a1f8b32af001c15ce3c6be2364826b1ca35b6caa
Author:     Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
AuthorDate: Fri Sep 22 22:27:15 2023 +0000
Commit:     Julien Grall <jgrall@xxxxxxxxxx>
CommitDate: Wed Sep 27 11:34:55 2023 +0100

    ARM: GICv3 ITS: flush caches for newly allocated ITT
    
    ITS manages Device Tables and Interrupt Translation Tables on its own,
    so generally we are not interested in maintaining any coherence with
    CPU's view of those memory regions, except one case: ITS requires that
    Interrupt Translation Tables should be initialized with
    zeroes. Existing code already does this, but it does not cleans
    caches afterwards. This means that ITS may see un-initialized ITT and
    CPU can overwrite portions of ITT later, when it finally decides to
    flush caches. Visible effect of this issue that there are not
    interrupts delivered from a device.
    
    Fix this by calling clean_and_invalidate_dcache_va_range() for newly
    allocated ITT.
    
    Fixes: 69082e1c210d ("ARM: GICv3 ITS: introduce device mapping")
    Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@xxxxxxxx>
    Tested-by: Stewart Hildebrand <stewart.hildebrand@xxxxxxx>
    Reviewed-by: Julien Grall <jgrall@xxxxxxxxxx>
    Release-acked-by: Henry Wang <Henry.Wang@xxxxxxx>
---
 xen/arch/arm/gic-v3-its.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c
index 3aa4edda10..8afcd9783b 100644
--- a/xen/arch/arm/gic-v3-its.c
+++ b/xen/arch/arm/gic-v3-its.c
@@ -685,6 +685,9 @@ int gicv3_its_map_guest_device(struct domain *d,
     if ( !itt_addr )
         goto out_unlock;
 
+    clean_and_invalidate_dcache_va_range(itt_addr,
+                                         nr_events * hw_its->itte_size);
+
     dev = xzalloc(struct its_device);
     if ( !dev )
         goto out_unlock;
--
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