[xen staging] x86/cpuid: Advertise SERIALIZE by default to guests

[patchbot@xxxxxxx]

commit 4feacc95265a3d786753ed1532c77eb382630f78
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Tue Dec 14 20:04:17 2021 +0000
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Thu Dec 16 20:27:13 2021 +0000

    x86/cpuid: Advertise SERIALIZE by default to guests
    
    I've played with SERIALIZE, TSXLDTRK, MOVDIRI and MOVDIR64 on real hardware,
    and they all seem fine, including emulation support.
    
    SERIALIZE exists specifically to have a userspace usable serialising 
operation
    without other side effects.  (The only other two choices are CPUID which is 
a
    VMExit under virt and clobbers 4 registers, and IRET-to-self which very slow
    and consumes content from the stack.)
    
    TSXLDTRK is a niche TSX feature, and TSX itself is niche outside of demos of
    speculative sidechannels.  Leave the feature opt-in until a usecase is 
found,
    in an effort to preempt the multiple person years of effort it has taken to
    mop up TSX issues impacting every processor line.
    
    MOVDIRI and MOVDIR64 are harder to judge.  They're architectural building
    blocks towards ENQCMD{,S} without obvious usecases on their own.  They're of
    no use to domains without PCI devices, so leave them opt-in for now.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/include/public/arch-x86/cpufeatureset.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/include/public/arch-x86/cpufeatureset.h 
b/xen/include/public/arch-x86/cpufeatureset.h
index 647ee9e5e2..0b39937556 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -278,7 +278,7 @@ XEN_CPUFEATURE(SRBDS_CTRL,    9*32+ 9) /*   
MSR_MCU_OPT_CTRL and RNGDS_MITG_DIS.
 XEN_CPUFEATURE(MD_CLEAR,      9*32+10) /*A  VERW clears microarchitectural 
buffers */
 XEN_CPUFEATURE(RTM_ALWAYS_ABORT, 9*32+11) /*! June 2021 TSX defeaturing in 
microcode. */
 XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */
-XEN_CPUFEATURE(SERIALIZE,     9*32+14) /*a  SERIALIZE insn */
+XEN_CPUFEATURE(SERIALIZE,     9*32+14) /*A  SERIALIZE insn */
 XEN_CPUFEATURE(TSXLDTRK,      9*32+16) /*a  TSX load tracking suspend/resume 
insns */
 XEN_CPUFEATURE(CET_IBT,       9*32+20) /*   CET - Indirect Branch Tracking */
 XEN_CPUFEATURE(IBRSB,         9*32+26) /*A  IBRS and IBPB support (used by 
Intel) */
--
generated by git-patchbot for /home/xen/git/xen.git#staging