[xen staging] x86/AMD: drop MSR_K7_HWCR

[patchbot@xxxxxxx]

commit 836314747b0fd1688fc9526f7c73fd9313ba82f3
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Fri Jul 9 08:30:35 2021 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Fri Jul 9 08:30:35 2021 +0200

    x86/AMD: drop MSR_K7_HWCR
    
    We don't support any K7 (32-bit only) hardware anymore, and the MSR is
    accessible as MSR_K8_HWCR as well. Using the K7 name was particularly
    odd for Hygon as well as in a Fam0F-specific piece of code.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
 xen/arch/x86/cpu/amd.c          | 8 ++++----
 xen/arch/x86/cpu/hygon.c        | 4 ++--
 xen/include/asm-x86/msr-index.h | 1 -
 3 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 83b33047b7..2260eef3aa 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -694,9 +694,9 @@ static void init_amd(struct cpuinfo_x86 *c)
         * Errata 122 for all steppings (F+ have it disabled by default)
         */
        if (c->x86 == 15) {
-               rdmsrl(MSR_K7_HWCR, value);
+               rdmsrl(MSR_K8_HWCR, value);
                value |= 1 << 6;
-               wrmsrl(MSR_K7_HWCR, value);
+               wrmsrl(MSR_K8_HWCR, value);
        }
 
        /*
@@ -928,9 +928,9 @@ static void init_amd(struct cpuinfo_x86 *c)
        }
 
        if (cpu_has(c, X86_FEATURE_EFRO)) {
-               rdmsr(MSR_K7_HWCR, l, h);
+               rdmsr(MSR_K8_HWCR, l, h);
                l |= (1 << 27); /* Enable read-only APERF/MPERF bit */
-               wrmsr(MSR_K7_HWCR, l, h);
+               wrmsr(MSR_K8_HWCR, l, h);
        }
 
        /* Prevent TSC drift in non single-processor, single-core platforms. */
diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c
index 2272e1113f..67e23c5df9 100644
--- a/xen/arch/x86/cpu/hygon.c
+++ b/xen/arch/x86/cpu/hygon.c
@@ -70,9 +70,9 @@ static void init_hygon(struct cpuinfo_x86 *c)
                __set_bit(X86_FEATURE_ARAT, c->x86_capability);
 
        if (cpu_has(c, X86_FEATURE_EFRO)) {
-               rdmsrl(MSR_K7_HWCR, value);
+               rdmsrl(MSR_K8_HWCR, value);
                value |= (1 << 27); /* Enable read-only APERF/MPERF bit */
-               wrmsrl(MSR_K7_HWCR, value);
+               wrmsrl(MSR_K8_HWCR, value);
        }
 
        amd_log_freq(c);
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 7e38c257d8..a14841055f 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -297,7 +297,6 @@
 #define MSR_K7_CLK_CTL                 0xc001001b
 #define MSR_K8_TOP_MEM2                        0xc001001d
 
-#define MSR_K7_HWCR                    0xc0010015
 #define MSR_K8_HWCR                    0xc0010015
 #define K8_HWCR_TSC_FREQ_SEL           (1ULL << 24)
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging