[xen staging] x86/PV32: avoid TLB flushing after mod_l3_entry()

[patchbot@xxxxxxx]

commit bed7e6cad30ec8db0c9ce9a1676856e9dc4c39da
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Fri Apr 9 09:19:18 2021 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Fri Apr 9 09:19:18 2021 +0200

    x86/PV32: avoid TLB flushing after mod_l3_entry()
    
    32-bit guests may not depend upon the side effect of using ordinary
    4-level paging when running on a 64-bit hypervisor. For L3 entry updates
    to take effect, they have to use a CR3 reload. Therefore there's no need
    to issue a paging structure invalidating TLB flush in this case.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Acked-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
---
 xen/arch/x86/mm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c
index 44e4c4cf1f..69d04ad809 100644
--- a/xen/arch/x86/mm.c
+++ b/xen/arch/x86/mm.c
@@ -4069,7 +4069,8 @@ long do_mmu_update(
                                       cmd == MMU_PT_UPDATE_PRESERVE_AD, v);
                     if ( !rc &&
                          (page->u.inuse.type_info & PGT_count_mask) >
-                         1 + !!(page->u.inuse.type_info & PGT_pinned) )
+                         1 + !!(page->u.inuse.type_info & PGT_pinned) &&
+                         !is_pv_32bit_domain(pt_owner) )
                         flush_linear_pt = true;
                     break;
 
--
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