[qemu-xen staging] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()

[patchbot@xxxxxxx]

commit 1989205c4e973bc7f9fac0ce0700993f30582538
Author:     Frank Chang <frank.chang@xxxxxxxxxx>
AuthorDate: Fri Jul 10 18:48:16 2020 +0800
Commit:     Alistair Francis <alistair.francis@xxxxxxx>
CommitDate: Mon Jul 13 17:25:37 2020 -0700

    target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
    
    Signed-off-by: Frank Chang <frank.chang@xxxxxxxxxx>
    Reviewed-by: Richard Henderson <richard.henderson@xxxxxxxxxx>
    Message-Id: <20200710104920.13550-3-frank.chang@xxxxxxxxxx>
    Signed-off-by: Alistair Francis <alistair.francis@xxxxxxx>
---
 target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
b/target/riscv/insn_trans/trans_rvv.inc.c
index 433cdacbe1..7cd08f0868 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -937,7 +937,7 @@ static void gen_vec_rsub8_i64(TCGv_i64 d, TCGv_i64 a, 
TCGv_i64 b)
 
 static void gen_vec_rsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
 {
-    tcg_gen_vec_sub8_i64(d, b, a);
+    tcg_gen_vec_sub16_i64(d, b, a);
 }
 
 static void gen_rsub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
--
generated by git-patchbot for /home/xen/git/qemu-xen.git#staging