[Xen-changelog] [xen staging] x86/spec-ctrl: Annotate remaining model names

[patchbot@xxxxxxx]

commit 6fc2c7f54811dc41e629e18715ead4548ed4fae7
Author:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
AuthorDate: Thu Oct 3 15:04:03 2019 +0100
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Fri Oct 4 18:28:36 2019 +0100

    x86/spec-ctrl: Annotate remaining model names
    
    The names in retpoline_safe() are copied from should_use_eager_fpu().  The
    names in mds_calculations() come partly from Linux's intel-family.h, and
    partly from conversations with Intel.
    
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
    Release-acked-by: Juergen Gross <jgross@xxxxxxxx>
---
 xen/arch/x86/spec_ctrl.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 4761be81bd..731d5a767b 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -505,13 +505,13 @@ static bool __init retpoline_safe(uint64_t caps)
         /*
          * Skylake, Kabylake and Cannonlake processors are not retpoline-safe.
          */
-    case 0x4e:
-    case 0x55:
-    case 0x5e:
-    case 0x66:
-    case 0x67:
-    case 0x8e:
-    case 0x9e:
+    case 0x4e: /* Skylake M */
+    case 0x55: /* Skylake X */
+    case 0x5e: /* Skylake D */
+    case 0x66: /* Cannonlake */
+    case 0x67: /* Cannonlake? */
+    case 0x8e: /* Kabylake M */
+    case 0x9e: /* Kabylake D */
         return false;
 
         /*
@@ -842,10 +842,10 @@ static __init void mds_calculations(uint64_t caps)
     case 0x4c: /* Cherrytrail / Brasswell */
     case 0x4d: /* Avaton / Rangely (Silvermont) */
     case 0x5a: /* Moorefield */
-    case 0x5d:
-    case 0x65:
-    case 0x6e:
-    case 0x75:
+    case 0x5d: /* SoFIA 3G Granite/ES2.1 */
+    case 0x65: /* SoFIA LTE AOSP */
+    case 0x6e: /* Cougar Mountain */
+    case 0x75: /* Lightning Mountain */
         /*
          * Knights processors (which are based on the Silvermont/Airmont
          * microarchitecture) are similarly only affected by the Store Buffer
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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