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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen staging] x86/CPUID: support leaf 7 subleaf 1 / AVX512_BF16
commit 97e4ebdcd765f9e5296e58d5071225369a45a7ad
Author: Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Tue May 21 15:43:00 2019 +0200
Commit: Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Tue May 21 15:43:00 2019 +0200
x86/CPUID: support leaf 7 subleaf 1 / AVX512_BF16
The AVX512_BF16 feature flag resides in this so far blank sub-leaf.
Expand infrastructure accordingly.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
tools/libxl/libxl_cpuid.c | 2 ++
tools/misc/xen-cpuid.c | 6 ++++++
xen/arch/x86/cpu/common.c | 10 ++++++++--
xen/include/public/arch-x86/cpufeatureset.h | 3 +++
xen/include/xen/lib/x86/cpuid.h | 12 +++++++++++-
xen/tools/gen-cpuid.py | 2 +-
6 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
index 4e3656fa35..a8d07fac50 100644
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -218,6 +218,8 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list
*cpuid, const char* str)
{"arch-caps", 0x00000007, 0, CPUID_REG_EDX, 29, 1},
{"ssbd", 0x00000007, 0, CPUID_REG_EDX, 31, 1},
+ {"avx512-bf16", 0x00000007, 1, CPUID_REG_EAX, 5, 1},
+
{"lahfsahf", 0x80000001, NA, CPUID_REG_ECX, 0, 1},
{"cmplegacy", 0x80000001, NA, CPUID_REG_ECX, 1, 1},
{"svm", 0x80000001, NA, CPUID_REG_ECX, 2, 1},
diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index 9d93eeed24..b0db0525a9 100644
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -164,6 +164,11 @@ static const char *const str_7d0[32] =
/* 30 */ [31] = "ssbd",
};
+static const char *const str_7a1[32] =
+{
+ /* 4 */ [ 5] = "avx512_bf16",
+};
+
static const struct {
const char *name;
const char *abbr;
@@ -180,6 +185,7 @@ static const struct {
{ "0x80000007.edx", "e7d", str_e7d },
{ "0x80000008.ebx", "e8b", str_e8b },
{ "0x00000007:0.edx", "7d0", str_7d0 },
+ { "0x00000007:1.eax", "7a1", str_7a1 },
};
#define COL_ALIGN "18"
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 43cfdc8155..33f5d32557 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -391,11 +391,17 @@ static void generic_identify(struct cpuinfo_x86 *c)
= cpuid_ebx(0x80000008);
/* Intel-defined flags: level 0x00000007 */
- if ( c->cpuid_level >= 0x00000007 )
- cpuid_count(0x00000007, 0, &tmp,
+ if ( c->cpuid_level >= 0x00000007 ) {
+ cpuid_count(0x00000007, 0, &eax,
&c->x86_capability[cpufeat_word(X86_FEATURE_FSGSBASE)],
&c->x86_capability[cpufeat_word(X86_FEATURE_PKU)],
&c->x86_capability[cpufeat_word(X86_FEATURE_AVX512_4VNNIW)]);
+ if (eax > 0)
+ cpuid_count(0x00000007, 1,
+
&c->x86_capability[cpufeat_word(X86_FEATURE_AVX512_BF16)],
+ &tmp, &tmp, &tmp);
+ }
+
if (c->cpuid_level >= 0xd)
cpuid_count(0xd, 1,
&c->x86_capability[cpufeat_word(X86_FEATURE_XSAVEOPT)],
diff --git a/xen/include/public/arch-x86/cpufeatureset.h
b/xen/include/public/arch-x86/cpufeatureset.h
index e4651b4434..54ff82146d 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -250,6 +250,9 @@ XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD
and L1D flush. */
XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /* IA32_ARCH_CAPABILITIES MSR */
XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */
+/* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */
+XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /* AVX512 BFloat16 Instructions */
+
#endif /* XEN_CPUFEATURE */
/* Clean up from a default include. Close the enum (for C). */
diff --git a/xen/include/xen/lib/x86/cpuid.h b/xen/include/xen/lib/x86/cpuid.h
index 022757f995..252d2c978d 100644
--- a/xen/include/xen/lib/x86/cpuid.h
+++ b/xen/include/xen/lib/x86/cpuid.h
@@ -14,6 +14,7 @@
#define FEATURESET_e7d 7 /* 0x80000007.edx */
#define FEATURESET_e8b 8 /* 0x80000008.ebx */
#define FEATURESET_7d0 9 /* 0x00000007:0.edx */
+#define FEATURESET_7a1 10 /* 0x00000007:1.eax */
struct cpuid_leaf
{
@@ -79,7 +80,7 @@ const char *x86_cpuid_vendor_to_str(unsigned int vendor);
#define CPUID_GUEST_NR_BASIC (0xdu + 1)
#define CPUID_GUEST_NR_CACHE (5u + 1)
-#define CPUID_GUEST_NR_FEAT (0u + 1)
+#define CPUID_GUEST_NR_FEAT (1u + 1)
#define CPUID_GUEST_NR_TOPO (1u + 1)
#define CPUID_GUEST_NR_XSTATE (62u + 1)
#define CPUID_GUEST_NR_EXTD_INTEL (0x8u + 1)
@@ -177,6 +178,13 @@ struct cpuid_policy
struct { DECL_BITFIELD(7d0); };
};
};
+ struct {
+ /* Subleaf 1. */
+ union {
+ uint32_t _7a1;
+ struct { DECL_BITFIELD(7a1); };
+ };
+ };
} feat;
/* Extended topology enumeration: 0x0000000B[xx] */
@@ -280,6 +288,7 @@ static inline void cpuid_policy_to_featureset(
fs[FEATURESET_e7d] = p->extd.e7d;
fs[FEATURESET_e8b] = p->extd.e8b;
fs[FEATURESET_7d0] = p->feat._7d0;
+ fs[FEATURESET_7a1] = p->feat._7a1;
}
/* Fill in a CPUID policy from a featureset bitmap. */
@@ -296,6 +305,7 @@ static inline void cpuid_featureset_to_policy(
p->extd.e7d = fs[FEATURESET_e7d];
p->extd.e8b = fs[FEATURESET_e8b];
p->feat._7d0 = fs[FEATURESET_7d0];
+ p->feat._7a1 = fs[FEATURESET_7a1];
}
const uint32_t *x86_cpuid_lookup_deep_deps(uint32_t feature);
diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index 67ec54b183..8f6b977df0 100755
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -270,7 +270,7 @@ def crunch_numbers(state):
# AVX512 extensions acting solely on vectors of bytes/words are made
# dependents of AVX512BW (as to requiring wider than 16-bit mask
# registers), despite the SDM not formally making this connection.
- AVX512BW: [AVX512_VBMI],
+ AVX512BW: [AVX512_BF16, AVX512_VBMI],
# The features:
# * Single Thread Indirect Branch Predictors
--
generated by git-patchbot for /home/xen/git/xen.git#staging
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