[Xen-changelog] [xen staging] xen/arm: gic-v2: deactivate interrupts during initialization

[patchbot@xxxxxxx]

commit b4df73de493954c44f240f78779c9bd3782e1572
Author:     Stefano Stabellini <sstabellini@xxxxxxxxxx>
AuthorDate: Tue Feb 5 13:38:53 2019 -0800
Commit:     Stefano Stabellini <sstabellini@xxxxxxxxxx>
CommitDate: Thu Feb 7 09:14:39 2019 -0800

    xen/arm: gic-v2: deactivate interrupts during initialization
    
    Interrupts could be ACTIVE at boot. Make sure to deactivate them during
    initialization.
    
    Signed-off-by: Stefano Stabellini <stefanos@xxxxxxxxxx>
    Reviewed-by: Julien Grall <julien.grall@xxxxxxx>
    CC: julien.grall@xxxxxxx
    CC: peng.fan@xxxxxxx
    CC: jgross@xxxxxxxx
---
 xen/arch/arm/gic-v2.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index e9fb8a01ab..256988c665 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -379,7 +379,10 @@ static void __init gicv2_dist_init(void)
 
     /* Disable all global interrupts */
     for ( i = 32; i < nr_lines; i += 32 )
+    {
         writel_gicd(~0x0, GICD_ICENABLER + (i / 32) * 4);
+        writel_gicd(~0x0, GICD_ICACTIVER + (i / 32) * 4);
+    }
 
     /* Turn on the distributor */
     writel_gicd(GICD_CTL_ENABLE, GICD_CTLR);
@@ -394,6 +397,7 @@ static void gicv2_cpu_init(void)
     /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so
      * even though they are controlled with GICD registers, they must
      * be set up here with the other per-cpu state. */
+    writel_gicd(0xffffffff, GICD_ICACTIVER); /* Diactivate PPIs and SGIs */
     writel_gicd(0xffff0000, GICD_ICENABLER); /* Disable all PPI */
     writel_gicd(0x0000ffff, GICD_ISENABLER); /* Enable all SGI */
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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