[Xen-changelog] [xen staging] xen/arm: Ignore write to GICD_ISACTIVERn registers (vgic-v2)

[patchbot@xxxxxxx]

commit 25f9e80201f3688e0c4d5c4e43e4b6143b441c52
Author:     Mirela Simonovic <mirela.simonovic@xxxxxxxxxx>
AuthorDate: Fri Jun 1 15:17:42 2018 +0200
Commit:     Julien Grall <julien.grall@xxxxxxx>
CommitDate: Tue Jun 5 19:07:24 2018 +0100

    xen/arm: Ignore write to GICD_ISACTIVERn registers (vgic-v2)
    
    Guests attempt to write into these registers on resume (for example Linux).
    Without this patch a data abort exception will be raised to the guest.
    This patch handles the write access by ignoring it, but only if the value
    to be written is zero. This should be fine because reading these registers
    is already handled as 'read as zero'.
    
    Signed-off-by: Mirela Simonovic <mirela.simonovic@xxxxxxxxxx>
    Reviewed-by: Julien Grall <julien.grall@xxxxxxx>
---
 xen/arch/arm/vgic-v2.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c
index 646d1f3d12..f6c11f1e41 100644
--- a/xen/arch/arm/vgic-v2.c
+++ b/xen/arch/arm/vgic-v2.c
@@ -485,6 +485,8 @@ static int vgic_v2_distr_mmio_write(struct vcpu *v, 
mmio_info_t *info,
 
     case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVERN):
         if ( dabt.size != DABT_WORD ) goto bad_width;
+        if ( r == 0 )
+            goto write_ignore_32;
         printk(XENLOG_G_ERR
                "%pv: vGICD: unhandled word write %#"PRIregister" to 
ISACTIVER%d\n",
                v, r, gicd_reg - GICD_ISACTIVER);
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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