[Xen-changelog] [xen stable-4.5] arm64: fix incorrect memory region size in TCR_EL2

[patchbot@xxxxxxx]

commit bdf3ef18a3f5d7f2e6b198838f6e77f237d3e3f2
Author:     Shanker Donthineni <shankerd@xxxxxxxxxxxxxx>
AuthorDate: Thu Mar 17 13:46:58 2016 +0100
Commit:     Stefano Stabellini <sstabellini@xxxxxxxxxx>
CommitDate: Thu Dec 1 14:07:53 2016 -0800

    arm64: fix incorrect memory region size in TCR_EL2
    
    The maximum and minimum values for TxSZ depend on level of
    translation as per AArch64 Virtual Memory System Architecture.
    According to ARM specification DDI0487A_h (sec D4.2.2, page 1752),
    the minimum TxSZ value is 16. If TxSZ is programmed to a value
    smaller than 16 then it is IMPLEMENTATION DEFINED.
    
    This patch sets T0SZ to (64-48)bits since XEN uses all 4 levels
    to cover 48bit (256TB) virtual address instead of value zero.
    
    Signed-off-by: Shanker Donthineni <shankerd@xxxxxxxxxxxxxx>
    Acked-by: Julien Grall <julien.grall@xxxxxxx>
---
 xen/arch/arm/arm64/head.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index 4bf85ff..fd12fee 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -342,8 +342,8 @@ skip_bss:
          * Top byte is used
          * PT walks use Inner-Shareable accesses,
          * PT walks are write-back, write-allocate in both cache levels,
-         * Full 64-bit address space goes through this table. */
-        ldr   x0, 
=(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0))
+         * 48-bit virtual address space goes through this table. */
+        ldr   x0, 
=(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(64-48))
         /* ID_AA64MMFR0_EL1[3:0] (PARange) corresponds to TCR_EL2[18:16] (PS) 
*/
         mrs   x1, ID_AA64MMFR0_EL1
         bfi   x0, x1, #16, #3
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.5

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