[Xen-changelog] [xen stable-4.6] x86/PV: make PMU MSR handling consistent

[patchbot@xxxxxxx]

commit 1663655cd05bc4db1344907b7404217453b79b66
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Tue Sep 6 11:51:59 2016 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Tue Sep 6 11:51:59 2016 +0200

    x86/PV: make PMU MSR handling consistent
    
    So far accesses to Intel MSRs on an AMD system fall through to the
    default case, while accesses to AMD MSRs on an Intel system bail (in
    the RDMSR case without updating EAX and EDX). Make the "AMD MSRs on
    Intel" case match the "Intel MSR on AMD" one.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Reviewed-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>
    Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    master commit: bea64b3ed25864b90a41e1ca6eeb5a58895bb751
    master date: 2016-09-02 14:19:29 +0200
---
 xen/arch/x86/traps.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 16d979d..7e8bf89 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2664,8 +2664,8 @@ static int emulate_privileged_op(struct cpu_user_regs 
*regs)
 
                     if ( vpmu_do_wrmsr(regs->ecx, msr_content, 0) )
                         goto fail;
+                    break;
                 }
-                break;
             }
             /*FALLTHROUGH*/
 
@@ -2799,8 +2799,8 @@ static int emulate_privileged_op(struct cpu_user_regs 
*regs)
 
                     regs->eax = (uint32_t)val;
                     regs->edx = (uint32_t)(val >> 32);
+                    break;
                 }
-                break;
             }
             /*FALLTHROUGH*/
 
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.6

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