[Xen-changelog] [xen master] xen/arm: vgic-v2: Implement correctly ICFGR{0, 1} read-only

[patchbot@xxxxxxx]

commit afbbf2c8f638ba406b6f002fffe73f5761a5b658
Author:     Julien Grall <julien.grall@xxxxxxxxxx>
AuthorDate: Wed Nov 18 17:27:56 2015 +0000
Commit:     Ian Campbell <ian.campbell@xxxxxxxxxx>
CommitDate: Wed Nov 25 12:29:27 2015 +0000

    xen/arm: vgic-v2: Implement correctly ICFGR{0, 1} read-only
    
    Each ITARGETSR register is 4-bytes wide and the offset is in bytes.
    
    The current implementation is computing the offset of ICFGR1 and ICFG2
    wrongly result to emulate only the first 2 byte of the ICFGR<n> range
    read-only. The rest will be treated as read-write.
    
    For convenience introduce ITARGETSR1 and ITARGETSR2.
    
    Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    [ ijc -- typoes in commit message ]
---
 xen/arch/arm/vgic-v2.c    |    6 ++++--
 xen/include/asm-arm/gic.h |    2 ++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c
index c94f0f3..4fb954b 100644
--- a/xen/arch/arm/vgic-v2.c
+++ b/xen/arch/arm/vgic-v2.c
@@ -507,10 +507,12 @@ static int vgic_v2_distr_mmio_write(struct vcpu *v, 
mmio_info_t *info,
 
     case GICD_ICFGR: /* SGIs */
         goto write_ignore_32;
-    case GICD_ICFGR + 1: /* PPIs */
+
+    case GICD_ICFGR1:
         /* It is implementation defined if these are writeable. We chose not */
         goto write_ignore_32;
-    case GICD_ICFGR + 2 ... GICD_ICFGRN: /* SPIs */
+
+    case GICD_ICFGR2 ... GICD_ICFGRN: /* SPIs */
         if ( dabt.size != DABT_WORD ) goto bad_width;
         rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD);
         if ( rank == NULL) goto write_ignore;
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 3064d1c..42a2eec 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -46,6 +46,8 @@
 #define GICD_ITARGETSR8 (0x820)
 #define GICD_ITARGETSRN (0xBF8)
 #define GICD_ICFGR      (0xC00)
+#define GICD_ICFGR1     (0xC04)
+#define GICD_ICFGR2     (0xC08)
 #define GICD_ICFGRN     (0xCFC)
 #define GICD_NSACR      (0xE00)
 #define GICD_NSACRN     (0xEFC)
--
generated by git-patchbot for /home/xen/git/xen.git#master

_______________________________________________
Xen-changelog mailing list
Xen-changelog@xxxxxxxxxxxxx
http://lists.xensource.com/xen-changelog