[Xen-changelog] [xen stable-4.4] xen: arm: Implement OSDLR_EL1 trap as RAZ/WO.

[patchbot@xxxxxxx]

commit c2800a8f93c828671ee4b2517accea8c546eb883
Author:     Ian Campbell <ian.campbell@xxxxxxxxxx>
AuthorDate: Fri Jun 13 13:15:04 2014 +0100
Commit:     Ian Campbell <ian.campbell@xxxxxxxxxx>
CommitDate: Wed Jul 2 10:47:46 2014 +0100

    xen: arm: Implement OSDLR_EL1 trap as RAZ/WO.
    
    I'm not sure why this wasn't added at the same time as the other
    debug registers.
    
    Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    Acked-by: Julien Grall <julien.grall@xxxxxxxxxx>
    (cherry picked from commit 92b0b80f0d2d29d0e80bf35ea839ed6058b7f0fa)
---
 xen/arch/arm/traps.c          |    4 +++-
 xen/include/asm-arm/sysregs.h |    1 +
 2 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 04720b1..e2e2db3 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1595,9 +1595,11 @@ static void do_sysreg(struct cpu_user_regs *regs,
     /* - Breakpoints */
     HSR_SYSREG_DBG_CASES(DBGBVR):
     HSR_SYSREG_DBG_CASES(DBGBCR):
-    /* -  Watchpoints */
+    /* - Watchpoints */
     HSR_SYSREG_DBG_CASES(DBGWVR):
     HSR_SYSREG_DBG_CASES(DBGWCR):
+    /* - Double Lock Register */
+    case HSR_SYSREG_OSDLR_EL1:
         if ( hsr.sysreg.read )
             *x = 0;
         /* else: write ignored */
diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h
index 4a4de34..b00871c 100644
--- a/xen/include/asm-arm/sysregs.h
+++ b/xen/include/asm-arm/sysregs.h
@@ -42,6 +42,7 @@
 
 #define HSR_SYSREG_MDSCR_EL1      HSR_SYSREG(2,0,c0,c2,2)
 #define HSR_SYSREG_OSLAR_EL1      HSR_SYSREG(2,0,c1,c0,4)
+#define HSR_SYSREG_OSDLR_EL1      HSR_SYSREG(2,0,c1,c3,4)
 
 #define HSR_SYSREG_DBGBVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,4)
 #define HSR_SYSREG_DBGBCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,5)
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.4

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