[Xen-changelog] [xen master] xen/arm: Save/restore GICH_VMCR on domain context switch

[patchbot@xxxxxxx]

commit 910b590601970440bdb135ed83fe28d8a755173e
Author:     Julien Grall <julien.grall@xxxxxxxxxx>
AuthorDate: Tue Feb 18 13:58:21 2014 +0000
Commit:     Ian Campbell <ian.campbell@xxxxxxxxxx>
CommitDate: Tue Feb 18 17:34:32 2014 +0000

    xen/arm: Save/restore GICH_VMCR on domain context switch
    
    GICH_VMCR register contains alias to important bits of GICV interface such 
as:
        - priority mask of the CPU
        - EOImode
        - ...
    
    We were safe because Linux guest always use the same value for this bits.
    When new guests will handle priority or change EOI mode, VCPU interrupt
    management will be in a wrong state.
    
    Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    Cc: George Dunlap <george.dunlap@xxxxxxxxxx>
---
 xen/arch/arm/gic.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 13bbf48..074624e 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -107,6 +107,7 @@ void gic_save_state(struct vcpu *v)
         v->arch.gic_lr[i] = GICH[GICH_LR + i];
     v->arch.lr_mask = this_cpu(lr_mask);
     v->arch.gic_apr = GICH[GICH_APR];
+    v->arch.gic_vmcr = GICH[GICH_VMCR];
     /* Disable until next VCPU scheduled */
     GICH[GICH_HCR] = 0;
     isb();
@@ -123,6 +124,7 @@ void gic_restore_state(struct vcpu *v)
     for ( i=0; i<nr_lrs; i++)
         GICH[GICH_LR + i] = v->arch.gic_lr[i];
     GICH[GICH_APR] = v->arch.gic_apr;
+    GICH[GICH_VMCR] = v->arch.gic_vmcr;
     GICH[GICH_HCR] = GICH_HCR_EN;
     isb();
 
--
generated by git-patchbot for /home/xen/git/xen.git#master

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