[Xen-changelog] [xen master] arm: correct vfp save/restore asm constraints

[patchbot@xxxxxxx]

commit 74d57ce43b2266b274ad89189ca3280c1e286883
Author:     Ian Campbell <ian.campbell@xxxxxxxxxx>
AuthorDate: Wed Jul 10 12:54:00 2013 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Wed Jul 10 12:54:00 2013 +0200

    arm: correct vfp save/restore asm constraints
    
    Some versions of gcc complain:
    > vfp.c: In function 'vfp_restore_state':
    > vfp.c:45:27: error: memory input 0 is not directly addressable
    > vfp.c:51:31: error: memory input 0 is not directly addressable
    
    There is no way to express the constraint we want (which is the address of 
the
    array, clobbering the whole array). Therefore we have to fake it up by using
    two constraints.
    
    Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    Acked-by: Will.Deacon@xxxxxxx
    Acked-by: Julien Grall <julien.grall@xxxxxxxxxx>
---
 xen/arch/arm/arm32/vfp.c |   17 +++++++++--------
 1 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/xen/arch/arm/arm32/vfp.c b/xen/arch/arm/arm32/vfp.c
index 6780131..0069acd 100644
--- a/xen/arch/arm/arm32/vfp.c
+++ b/xen/arch/arm/arm32/vfp.c
@@ -22,15 +22,15 @@ void vfp_save_state(struct vcpu *v)
     }
 
     /* Save {d0-d15} */
-    asm volatile("stc p11, cr0, %0, #32*4"
-                 : "=Q" (v->arch.vfp.fpregs1));
+    asm volatile("stc p11, cr0, [%1], #32*4"
+                 : "=Q" (*v->arch.vfp.fpregs1) : "r" (v->arch.vfp.fpregs1));
 
     /* 32 x 64 bits registers? */
     if ( (READ_CP32(MVFR0) & MVFR0_A_SIMD_MASK) == 2 )
     {
         /* Save {d16-d31} */
-        asm volatile("stcl p11, cr0, %0, #32*4"
-                     : "=Q" (v->arch.vfp.fpregs2));
+        asm volatile("stcl p11, cr0, [%1], #32*4"
+                     : "=Q" (*v->arch.vfp.fpregs2) : "r" 
(v->arch.vfp.fpregs2));
     }
 
     WRITE_CP32(v->arch.vfp.fpexc & ~(FPEXC_EN), FPEXC);
@@ -38,17 +38,18 @@ void vfp_save_state(struct vcpu *v)
 
 void vfp_restore_state(struct vcpu *v)
 {
+    //uint64_t test[16];
     WRITE_CP32(READ_CP32(FPEXC) | FPEXC_EN, FPEXC);
 
     /* Restore {d0-d15} */
-    asm volatile("ldc p11, cr0, %0, #32*4"
-                 : : "Q" (v->arch.vfp.fpregs1));
+    asm volatile("ldc p11, cr0, [%1], #32*4"
+                 : : "Q" (*v->arch.vfp.fpregs1), "r" (v->arch.vfp.fpregs1));
 
     /* 32 x 64 bits registers? */
     if ( (READ_CP32(MVFR0) & MVFR0_A_SIMD_MASK) == 2 ) /* 32 x 64 bits 
registers */
         /* Restore {d16-d31} */
-        asm volatile("ldcl p11, cr0, %0, #32*4"
-                     : : "Q" (v->arch.vfp.fpregs2));
+        asm volatile("ldcl p11, cr0, [%1], #32*4"
+                     : : "Q" (*v->arch.vfp.fpregs2), "r" 
(v->arch.vfp.fpregs2));
 
     if ( v->arch.vfp.fpexc & FPEXC_EX )
     {
--
generated by git-patchbot for /home/xen/git/xen.git#master

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