[Xen-changelog] [xen master] arm: fix comment in HTCR setup.

[patchbot@xxxxxxx]

commit 7186e6718e70250900f934f6f95a5c60edffbfa6
Author:     Tim Deegan <tim@xxxxxxx>
AuthorDate: Thu Mar 28 10:07:48 2013 +0000
Commit:     Ian Campbell <ian.campbell@xxxxxxxxxx>
CommitDate: Thu Apr 11 14:25:30 2013 +0100

    arm: fix comment in HTCR setup.
    
    Reported-by: Gihun Jung <gihun.jung@xxxxxxxxx>
    Signed-off-by: Tim Deegan <tim@xxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
---
 xen/arch/arm/arm32/head.S |    2 +-
 xen/arch/arm/arm64/head.S |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
index db3baa0..f2f581d 100644
--- a/xen/arch/arm/arm32/head.S
+++ b/xen/arch/arm/arm32/head.S
@@ -189,7 +189,7 @@ skip_bss:
 
         /* Set up the HTCR:
          * PT walks use Outer-Shareable accesses,
-         * PT walks are write-back, no-write-allocate in both cache levels,
+         * PT walks are write-back, write-allocate in both cache levels,
          * Full 32-bit address space goes through this table. */
         ldr   r0, =0x80002500
         mcr   CP32(r0, HTCR)
diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index b7ab251..bbde419 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -173,7 +173,7 @@ skip_bss:
          * PASize -- 4G
          * Top byte is used
          * PT walks use Outer-Shareable accesses,
-         * PT walks are write-back, no-write-allocate in both cache levels,
+         * PT walks are write-back, write-allocate in both cache levels,
          * Full 64-bit address space goes through this table. */
         ldr   x0, =0x80802500
         msr   tcr_el2, x0
--
generated by git-patchbot for /home/xen/git/xen.git#master

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