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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen master] xen: arm: handle 32-bit guest CP register traps on 64-bit hypervisor
commit db686bc7b006002d2c89df8dd6a5f5f6f4ee60c4
Author: Ian Campbell <ian.campbell@xxxxxxxxxx>
AuthorDate: Fri Feb 22 08:58:17 2013 +0000
Commit: Ian Campbell <ian.campbell@xxxxxxxxxx>
CommitDate: Fri Feb 22 12:14:55 2013 +0000
xen: arm: handle 32-bit guest CP register traps on 64-bit hypervisor
Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
Acked-by: Tim Deegan <tim@xxxxxxx>
---
xen/arch/arm/traps.c | 10 +++++++---
1 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 6be70fa..d1cf0e6 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -700,16 +700,16 @@ static void do_cp15_32(struct cpu_user_regs *regs,
"attempt to write to read-only register CLIDR\n");
domain_crash_synchronous();
}
- *r = READ_CP32(CLIDR);
+ *r = READ_SYSREG32(CLIDR_EL1);
break;
case HSR_CPREG32(CCSIDR):
if ( !cp32.read )
{
dprintk(XENLOG_ERR,
- "attempt to write to read-only register CSSIDR\n");
+ "attempt to write to read-only register CCSIDR\n");
domain_crash_synchronous();
}
- *r = READ_CP32(CCSIDR);
+ *r = READ_SYSREG32(CCSIDR_EL1);
break;
case HSR_CPREG32(DCCISW):
if ( cp32.read )
@@ -718,7 +718,11 @@ static void do_cp15_32(struct cpu_user_regs *regs,
"attempt to read from write-only register DCCISW\n");
domain_crash_synchronous();
}
+#ifdef CONFIG_ARM_32
WRITE_CP32(*r, DCCISW);
+#else
+ asm volatile("dc cisw, %0;" : : "r" (*r) : "memory");
+#endif
break;
case HSR_CPREG32(CNTP_CTL):
case HSR_CPREG32(CNTP_TVAL):
--
generated by git-patchbot for /home/xen/git/xen.git#master
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