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[Xen-changelog] [xen master] xen: arm64: TLB flushes



commit 5d7331690e317c3c926d0a9592f9d2840a1022d9
Author:     Ian Campbell <ian.campbell@xxxxxxxxxx>
AuthorDate: Fri Feb 22 08:57:49 2013 +0000
Commit:     Ian Campbell <ian.campbell@xxxxxxxxxx>
CommitDate: Fri Feb 22 12:14:51 2013 +0000

    xen: arm64: TLB flushes
    
    Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    Acked-by: Tim Deegan <tim@xxxxxxx>
---
 xen/include/asm-arm/arm32/flushtlb.h |   34 +++++++++++++++++
 xen/include/asm-arm/arm32/page.h     |   69 ++++++++++++++++++++++++++++++++++
 xen/include/asm-arm/arm64/flushtlb.h |   34 +++++++++++++++++
 xen/include/asm-arm/arm64/page.h     |   67 +++++++++++++++++++++++++++++++++
 xen/include/asm-arm/flushtlb.h       |   34 +++++------------
 xen/include/asm-arm/page.h           |   67 ++++-----------------------------
 6 files changed, 222 insertions(+), 83 deletions(-)

diff --git a/xen/include/asm-arm/arm32/flushtlb.h 
b/xen/include/asm-arm/arm32/flushtlb.h
new file mode 100644
index 0000000..e6dabd4
--- /dev/null
+++ b/xen/include/asm-arm/arm32/flushtlb.h
@@ -0,0 +1,34 @@
+#ifndef __ASM_ARM_ARM32_FLUSHTLB_H__
+#define __ASM_ARM_ARM32_FLUSHTLB_H__
+
+/* Flush local TLBs, current VMID only */
+static inline void flush_tlb_local(void)
+{
+    dsb();
+
+    WRITE_CP32((uint32_t) 0, TLBIALL);
+
+    dsb();
+    isb();
+}
+
+/* Flush local TLBs, all VMIDs, non-hypervisor mode */
+static inline void flush_tlb_all_local(void)
+{
+    dsb();
+
+    WRITE_CP32((uint32_t) 0, TLBIALLNSNH);
+
+    dsb();
+    isb();
+}
+
+#endif /* __ASM_ARM_ARM32_FLUSHTLB_H__ */
+/*
+ * Local variables:
+ * mode: C
+ * c-set-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h
new file mode 100644
index 0000000..073b8d1
--- /dev/null
+++ b/xen/include/asm-arm/arm32/page.h
@@ -0,0 +1,69 @@
+#ifndef __ARM_ARM32_PAGE_H__
+#define __ARM_ARM32_PAGE_H__
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Flush all hypervisor mappings from the TLB and branch predictor.
+ * This is needed after changing Xen code mappings.
+ *
+ * The caller needs to issue the necessary DSB and D-cache flushes
+ * before calling flush_xen_text_tlb.
+ */
+static inline void flush_xen_text_tlb(void)
+{
+    register unsigned long r0 asm ("r0");
+    asm volatile (
+        "isb;"                        /* Ensure synchronization with previous 
changes to text */
+        STORE_CP32(0, TLBIALLH)       /* Flush hypervisor TLB */
+        STORE_CP32(0, ICIALLU)        /* Flush I-cache */
+        STORE_CP32(0, BPIALL)         /* Flush branch predictor */
+        "dsb;"                        /* Ensure completion of TLB+BP flush */
+        "isb;"
+        : : "r" (r0) /*dummy*/ : "memory");
+}
+
+/*
+ * Flush all hypervisor mappings from the data TLB. This is not
+ * sufficient when changing code mappings or for self modifying code.
+ */
+static inline void flush_xen_data_tlb(void)
+{
+    register unsigned long r0 asm ("r0");
+    asm volatile("dsb;" /* Ensure preceding are visible */
+                 STORE_CP32(0, TLBIALLH)
+                 "dsb;" /* Ensure completion of the TLB flush */
+                 "isb;"
+                 : : "r" (r0) /* dummy */: "memory");
+}
+
+/*
+ * Flush a range of VA's hypervisor mappings from the data TLB. This is not
+ * sufficient when changing code mappings or for self modifying code.
+ */
+static inline void flush_xen_data_tlb_range_va(unsigned long va, unsigned long 
size)
+{
+    unsigned long end = va + size;
+    dsb(); /* Ensure preceding are visible */
+    while ( va < end ) {
+        asm volatile(STORE_CP32(0, TLBIMVAH)
+                     : : "r" (va) : "memory");
+        va += PAGE_SIZE;
+    }
+    dsb(); /* Ensure completion of the TLB flush */
+    isb();
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARM_ARM32_PAGE_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-set-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/arm64/flushtlb.h 
b/xen/include/asm-arm/arm64/flushtlb.h
new file mode 100644
index 0000000..ca74fe3
--- /dev/null
+++ b/xen/include/asm-arm/arm64/flushtlb.h
@@ -0,0 +1,34 @@
+#ifndef __ASM_ARM_ARM64_FLUSHTLB_H__
+#define __ASM_ARM_ARM64_FLUSHTLB_H__
+
+/* Flush local TLBs, current VMID only */
+static inline void flush_tlb_local(void)
+{
+    asm volatile(
+        "dsb sy;"
+        "tlbi vmalle1;"
+        "dsb sy;"
+        "isb;"
+        : : : "memory");
+}
+
+/* Flush local TLBs, all VMIDs, non-hypervisor mode */
+static inline void flush_tlb_all_local(void)
+{
+    asm volatile(
+        "dsb sy;"
+        "tlbi alle1;"
+        "dsb sy;"
+        "isb;"
+        : : : "memory");
+}
+
+#endif /* __ASM_ARM_ARM64_FLUSHTLB_H__ */
+/*
+ * Local variables:
+ * mode: C
+ * c-set-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h
new file mode 100644
index 0000000..636fb63
--- /dev/null
+++ b/xen/include/asm-arm/arm64/page.h
@@ -0,0 +1,67 @@
+#ifndef __ARM_ARM64_PAGE_H__
+#define __ARM_ARM64_PAGE_H__
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Flush all hypervisor mappings from the TLB
+ * This is needed after changing Xen code mappings.
+ *
+ * The caller needs to issue the necessary DSB and D-cache flushes
+ * before calling flush_xen_text_tlb.
+ */
+static inline void flush_xen_text_tlb(void)
+{
+    asm volatile (
+        "isb;"       /* Ensure synchronization with previous changes to text */
+        "tlbi   alle2;"                 /* Flush hypervisor TLB */
+        "ic     iallu;"                 /* Flush I-cache */
+        "dsb    sy;"                    /* Ensure completion of TLB flush */
+        "isb;"
+        : : : "memory");
+}
+
+/*
+ * Flush all hypervisor mappings from the data TLB. This is not
+ * sufficient when changing code mappings or for self modifying code.
+ */
+static inline void flush_xen_data_tlb(void)
+{
+    asm volatile (
+        "dsb    sy;"                    /* Ensure visibility of PTE writes */
+        "tlbi   alle2;"                 /* Flush hypervisor TLB */
+        "dsb    sy;"                    /* Ensure completion of TLB flush */
+        "isb;"
+        : : : "memory");
+}
+
+/*
+ * Flush a range of VA's hypervisor mappings from the data TLB. This is not
+ * sufficient when changing code mappings or for self modifying code.
+ */
+static inline void flush_xen_data_tlb_range_va(unsigned long va, unsigned long 
size)
+{
+    unsigned long end = va + size;
+    dsb(); /* Ensure preceding are visible */
+    while ( va < end ) {
+        asm volatile("tlbi vae2, %0;"
+                     : : "r" (va>>PAGE_SHIFT) : "memory");
+        va += PAGE_SIZE;
+    }
+    dsb(); /* Ensure completion of the TLB flush */
+    isb();
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARM_ARM64_PAGE_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-set-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/flushtlb.h b/xen/include/asm-arm/flushtlb.h
index 23376ac..329fbb4 100644
--- a/xen/include/asm-arm/flushtlb.h
+++ b/xen/include/asm-arm/flushtlb.h
@@ -1,5 +1,5 @@
-#ifndef __FLUSHTLB_H__
-#define __FLUSHTLB_H__
+#ifndef __ASM_ARM_FLUSHTLB_H__
+#define __ASM_ARM_FLUSHTLB_H__
 
 #include <xen/cpumask.h>
 
@@ -14,32 +14,18 @@ do {                                                        
            \
 
 #define tlbflush_current_time()                 (0)
 
-/* Flush local TLBs, current VMID only */
-static inline void flush_tlb_local(void)
-{
-    dsb();
-
-    WRITE_CP32((uint32_t) 0, TLBIALL);
-
-    dsb();
-    isb();
-}
-
-/* Flush local TLBs, all VMIDs, non-hypervisor mode */
-static inline void flush_tlb_all_local(void)
-{
-    dsb();
-
-    WRITE_CP32((uint32_t) 0, TLBIALLNSNH);
-
-    dsb();
-    isb();
-}
+#if defined(CONFIG_ARM_32)
+# include <asm/arm32/flushtlb.h>
+#elif defined(CONFIG_ARM_64)
+# include <asm/arm64/flushtlb.h>
+#else
+# error "unknown ARM variant"
+#endif
 
 /* Flush specified CPUs' TLBs */
 void flush_tlb_mask(const cpumask_t *mask);
 
-#endif /* __FLUSHTLB_H__ */
+#endif /* __ASM_ARM_FLUSHTLB_H__ */
 /*
  * Local variables:
  * mode: C
diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
index 45ded77..8909375 100644
--- a/xen/include/asm-arm/page.h
+++ b/xen/include/asm-arm/page.h
@@ -250,6 +250,14 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
         : : "r" (pte.bits), "r" (p) : "memory");
 }
 
+#if defined(CONFIG_ARM_32)
+# include <asm/arm32/page.h>
+#elif defined(CONFIG_ARM_64)
+# include <asm/arm64/page.h>
+#else
+# error "unknown ARM variant"
+#endif
+
 /* Architectural minimum cacheline size is 4 32-bit words. */
 #define MIN_CACHELINE_BYTES 16
 /* Actual cacheline size on the boot CPU. */
@@ -282,65 +290,6 @@ static inline void flush_xen_dcache_va_range(void *p, 
unsigned long size)
             : : "r" (_p), "m" (*_p));                                   \
 } while (0)
 
-
-/*
- * Flush all hypervisor mappings from the TLB and branch predictor.
- * This is needed after changing Xen code mappings.
- *
- * The caller needs to issue the necessary DSB and D-cache flushes
- * before calling flush_xen_text_tlb.
- */
-static inline void flush_xen_text_tlb(void)
-{
-    register unsigned long r0 asm ("r0");
-    asm volatile (
-        "isb;"                        /* Ensure synchronization with previous 
changes to text */
-        STORE_CP32(0, TLBIALLH)       /* Flush hypervisor TLB */
-        STORE_CP32(0, ICIALLU)        /* Flush I-cache */
-        STORE_CP32(0, BPIALL)         /* Flush branch predictor */
-        "dsb;"                        /* Ensure completion of TLB+BP flush */
-        "isb;"
-        : : "r" (r0) /*dummy*/ : "memory");
-}
-
-/*
- * Flush all hypervisor mappings from the data TLB. This is not
- * sufficient when changing code mappings or for self modifying code.
- */
-static inline void flush_xen_data_tlb(void)
-{
-    register unsigned long r0 asm ("r0");
-    asm volatile("dsb;" /* Ensure preceding are visible */
-                 STORE_CP32(0, TLBIALLH)
-                 "dsb;" /* Ensure completion of the TLB flush */
-                 "isb;"
-                 : : "r" (r0) /* dummy */: "memory");
-}
-
-/*
- * Flush a range of VA's hypervisor mappings from the data TLB. This is not
- * sufficient when changing code mappings or for self modifying code.
- */
-static inline void flush_xen_data_tlb_range_va(unsigned long va, unsigned long 
size)
-{
-    unsigned long end = va + size;
-    dsb(); /* Ensure preceding are visible */
-    while ( va < end ) {
-        asm volatile(STORE_CP32(0, TLBIMVAH)
-                     : : "r" (va) : "memory");
-        va += PAGE_SIZE;
-    }
-    dsb(); /* Ensure completion of the TLB flush */
-    isb();
-}
-
-/* Flush all non-hypervisor mappings from the TLB */
-static inline void flush_guest_tlb(void)
-{
-    register unsigned long r0 asm ("r0");
-    WRITE_CP32(r0 /* dummy */, TLBIALLNSNH);
-}
-
 /* Print a walk of an arbitrary page table */
 void dump_pt_walk(lpae_t *table, paddr_t addr);
 
--
generated by git-patchbot for /home/xen/git/xen.git#master

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