[Xen-changelog] [xen stable-4.2] x86/AMD: Enable WC+ memory type on family 10 processors

[patchbot@xxxxxxx]

commit c2f3fffa77d8029563d8aeeab212d7b38b24e48a
Author:     Boris Ostrovsky <boris.ostrovsky@xxxxxxx>
AuthorDate: Tue Feb 12 13:38:22 2013 +0100
Commit:     Boris Ostrovsky <boris.ostrovsky@xxxxxxx>
CommitDate: Tue Feb 12 13:38:22 2013 +0100

    x86/AMD: Enable WC+ memory type on family 10 processors
    
    In some cases BIOS may not enable WC+ memory type on family 10 processors,
    instead converting what would be WC+ memory to CD type. On guests using
    nested pages this could result in performance degradation. This patch
    enables WC+.
    
    Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxx>
    xen-unstable changeset: 26427:8f6dd5dc5d6c
    xen-unstable date: Fri Jan 18 11:20:58 UTC 2013
---
 xen/arch/x86/cpu/amd.c          |   13 +++++++++++++
 xen/include/asm-x86/msr-index.h |    5 +++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 4823bcd..a317fd1 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -534,6 +534,19 @@ static void __devinit init_amd(struct cpuinfo_x86 *c)
        }
 #endif
 
+       if (c->x86 == 0x10) {
+               /*
+                * On family 10h BIOS may not have properly enabled WC+
+                * support, causing it to be converted to CD memtype. This may
+                * result in performance degradation for certain nested-paging
+                * guests. Prevent this conversion by clearing bit 24 in
+                * MSR_F10_BU_CFG2.
+                */
+               rdmsrl(MSR_F10_BU_CFG2, value);
+               value &= ~(1ULL << 24);
+               wrmsrl(MSR_F10_BU_CFG2, value);
+       }
+
        /*
         * Family 0x12 and above processors have APIC timer
         * running in deep C states.
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 94d5493..0c9654c 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -215,8 +215,9 @@
 #define MSR_F10_MC4_MISC2              0xc0000409
 #define MSR_F10_MC4_MISC3              0xc000040A
 
-/* AMD Family10h MMU control MSRs */
-#define MSR_F10_BU_CFG                  0xc0011023
+/* AMD Family10h Bus Unit MSRs */
+#define MSR_F10_BU_CFG                 0xc0011023
+#define MSR_F10_BU_CFG2                0xc001102a
 
 /* Other AMD Fam10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.2

_______________________________________________
Xen-changelog mailing list
Xen-changelog@xxxxxxxxxxxxx
http://lists.xensource.com/xen-changelog