[Xen-changelog] [xen-4.1-testing] x86/AMD: Enable WC+ memory type on family 10 processors

[Xen patchbot-4.1-testing <patchbot@xxxxxxx>]

# HG changeset patch
# User Boris Ostrovsky <boris.ostrovsky@xxxxxxx>
# Date 1360672325 -3600
# Node ID 489802ca99548279d21d84261ec0789f352ec235
# Parent  1304461355287ca77d92ecf55bcdc25865e569ed
x86/AMD: Enable WC+ memory type on family 10 processors

In some cases BIOS may not enable WC+ memory type on family 10 processors,
instead converting what would be WC+ memory to CD type. On guests using
nested pages this could result in performance degradation. This patch
enables WC+.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxx>
xen-unstable changeset: 26427:8f6dd5dc5d6c
xen-unstable date: Fri Jan 18 11:20:58 UTC 2013
---


diff -r 130446135528 -r 489802ca9954 xen/arch/x86/cpu/amd.c
--- a/xen/arch/x86/cpu/amd.c    Thu Feb 07 14:26:37 2013 +0000
+++ b/xen/arch/x86/cpu/amd.c    Tue Feb 12 13:32:05 2013 +0100
@@ -661,6 +661,19 @@ static void __devinit init_amd(struct cp
        }
 #endif
 
+       if (c->x86 == 0x10) {
+               /*
+                * On family 10h BIOS may not have properly enabled WC+
+                * support, causing it to be converted to CD memtype. This may
+                * result in performance degradation for certain nested-paging
+                * guests. Prevent this conversion by clearing bit 24 in
+                * MSR_F10_BU_CFG2.
+                */
+               rdmsrl(MSR_F10_BU_CFG2, value);
+               value &= ~(1ULL << 24);
+               wrmsrl(MSR_F10_BU_CFG2, value);
+       }
+
        /*
         * Family 0x12 and above processors have APIC timer
         * running in deep C states.
diff -r 130446135528 -r 489802ca9954 xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h   Thu Feb 07 14:26:37 2013 +0000
+++ b/xen/include/asm-x86/msr-index.h   Tue Feb 12 13:32:05 2013 +0100
@@ -254,8 +254,9 @@
 #define MSR_F10_MC4_MISC2              0xc0000409
 #define MSR_F10_MC4_MISC3              0xc000040A
 
-/* AMD Family10h MMU control MSRs */
-#define MSR_F10_BU_CFG                  0xc0011023
+/* AMD Family10h Bus Unit MSRs */
+#define MSR_F10_BU_CFG                 0xc0011023
+#define MSR_F10_BU_CFG2                0xc001102a
 
 /* Other AMD Fam10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058

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