[Xen-changelog] [xen-unstable] vMCE: Implement AMD MSRs

[Xen patchbot-unstable <patchbot@xxxxxxx>]

# HG changeset patch
# User Christoph Egger <Christoph.Egger@xxxxxxx>
# Date 1350990654 25200
# Node ID 67c27013e191598543ccc1b8f8f1d533c7a5164b
# Parent  d642720e1ea996ce85203fc9718f64cf2cab0468
vMCE: Implement AMD MSRs

Signed-off-by: Christoph Egger <Christoph.Egger@xxxxxxx>
Committed-by: Keir Fraser <keir@xxxxxxx>
---


diff -r d642720e1ea9 -r 67c27013e191 xen/arch/x86/cpu/mcheck/amd_f10.c
--- a/xen/arch/x86/cpu/mcheck/amd_f10.c Tue Oct 23 09:14:27 2012 +0200
+++ b/xen/arch/x86/cpu/mcheck/amd_f10.c Tue Oct 23 04:10:54 2012 -0700
@@ -106,24 +106,43 @@ enum mcheck_type amd_f10_mcheck_init(str
 /* amd specific MCA MSR */
 int vmce_amd_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
 {
-        switch (msr) {
-        case MSR_F10_MC4_MISC1:
-        case MSR_F10_MC4_MISC2:
-        case MSR_F10_MC4_MISC3:
-                break;
-        }
+       switch (msr) {
+       case MSR_F10_MC4_MISC1: /* DRAM error type */
+               v->arch.vmce.bank[1].mci_misc = val; 
+               mce_printk(MCE_VERBOSE, "MCE: wr msr %#"PRIx64"\n", val);
+               break;
+       case MSR_F10_MC4_MISC2: /* Link error type */
+       case MSR_F10_MC4_MISC3: /* L3 cache error type */
+               /* ignore write: we do not emulate link and l3 cache errors
+                * to the guest.
+                */
+               mce_printk(MCE_VERBOSE, "MCE: wr msr %#"PRIx64"\n", val);
+               break;
+       default:
+               return 0;
+       }
 
-        return 1;
+       return 1;
 }
 
 int vmce_amd_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
 {
-        switch (msr) {
-        case MSR_F10_MC4_MISC1:
-        case MSR_F10_MC4_MISC2:
-        case MSR_F10_MC4_MISC3:
-                break;
-        }
+       switch (msr) {
+       case MSR_F10_MC4_MISC1: /* DRAM error type */
+               *val = v->arch.vmce.bank[1].mci_misc;
+               mce_printk(MCE_VERBOSE, "MCE: rd msr %#"PRIx64"\n", *val);
+               break;
+       case MSR_F10_MC4_MISC2: /* Link error type */
+       case MSR_F10_MC4_MISC3: /* L3 cache error type */
+               /* we do not emulate link and l3 cache
+                * errors to the guest.
+                */
+               *val = 0;
+               mce_printk(MCE_VERBOSE, "MCE: rd msr %#"PRIx64"\n", *val);
+               break;
+       default:
+               return 0;
+       }
 
-        return 1;
+       return 1;
 }

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