[Xen-changelog] [xen-4.1-testing] svm: Fake out the Bus Unit Config MSR on revF AMD CPUs

[Xen patchbot-4.1-testing <patchbot@xxxxxxx>]

# HG changeset patch
# User George Dunlap <george.dunlap@xxxxxxxxxxxxx>
# Date 1335878120 -3600
# Node ID a21938b58fc4323ca408dbcfe081770bc178f6ed
# Parent  b1e2ca715ae7f60ecb4bac84dcab48d9bb3006d9
svm: Fake out the Bus Unit Config MSR on revF AMD CPUs

Win2k8 x64 reads this MSR on revF chips, where it wasn't publically
available; it uses a magic constant in %rdi as a password, which we
don't have in rdmsr_safe().  Since we'll ignore the later writes, just
use a plausible value here (the reset value from rev10h chips) if the
real CPU didn't provide one.

Signed-off-by: George Dunlap <george.dunlap@xxxxxxxxxxxxx>
Committed-by: Keir Fraser <keir@xxxxxxx>
xen-unstable changeset:   24990:322300fd2ebd
xen-unstable date:        Thu Mar 08 09:17:21 2012 +0000

svm: amend c/s 24990:322300fd2ebd (fake BU_CFG MSR on AMD revF)

Let's restrict such a hack to the known affected family.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Acked-by: Keir Fraser <keir@xxxxxxx>
Acked-by: George Dunlap <george.dunlap@xxxxxxxxxxxxx>
xen-unstable changeset:   25058:f47d91cb0faa
xen-unstable date:        Thu Mar 15 15:09:18 2012 +0100
---


diff -r b1e2ca715ae7 -r a21938b58fc4 xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c        Tue May 01 14:13:58 2012 +0100
+++ b/xen/arch/x86/hvm/svm/svm.c        Tue May 01 14:15:20 2012 +0100
@@ -1197,6 +1197,18 @@ static int svm_msr_read_intercept(unsign
         if ( rdmsr_safe(msr, *msr_content) == 0 )
             break;
 
+        if ( boot_cpu_data.x86 == 0xf && msr == MSR_F10_BU_CFG )
+        {
+            /* Win2k8 x64 reads this MSR on revF chips, where it
+             * wasn't publically available; it uses a magic constant
+             * in %rdi as a password, which we don't have in
+             * rdmsr_safe().  Since we'll ignore the later writes,
+             * just use a plausible value here (the reset value from
+             * rev10h chips) if the real CPU didn't provide one. */
+            *msr_content = 0x0000000010200020ull;
+            break;
+        }
+
         goto gpf;
     }
 
diff -r b1e2ca715ae7 -r a21938b58fc4 xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h   Tue May 01 14:13:58 2012 +0100
+++ b/xen/include/asm-x86/msr-index.h   Tue May 01 14:15:20 2012 +0100
@@ -253,6 +253,9 @@
 #define MSR_F10_MC4_MISC2              0xc0000409
 #define MSR_F10_MC4_MISC3              0xc000040A
 
+/* AMD Family10h MMU control MSRs */
+#define MSR_F10_BU_CFG                  0xc0011023
+
 /* Other AMD Fam10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058
 #define FAM10H_MMIO_CONF_ENABLE         (1<<0)

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