[Xen-changelog] [xen-unstable] svm: Fake out the Bus Unit Config MSR on revF AMD CPUs

[Xen patchbot-unstable <patchbot@xxxxxxx>]

# HG changeset patch
# User George Dunlap <george.dunlap@xxxxxxxxxxxxx>
# Date 1331198241 0
# Node ID 322300fd2ebd7857b536531ccb79ceed5f799a36
# Parent  02216ba702b0a8f58871e1d9292b243f9b645b0b
svm: Fake out the Bus Unit Config MSR on revF AMD CPUs

Win2k8 x64 reads this MSR on revF chips, where it wasn't publically
available; it uses a magic constant in %rdi as a password, which we
don't have in rdmsr_safe().  Since we'll ignore the later writes, just
use a plausible value here (the reset value from rev10h chips) if the
real CPU didn't provide one.

Signed-off-by: George Dunlap <george.dunlap@xxxxxxxxxxxxx>
Committed-by: Keir Fraser <keir@xxxxxxx>
---


diff -r 02216ba702b0 -r 322300fd2ebd xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c        Thu Mar 08 09:16:09 2012 +0000
+++ b/xen/arch/x86/hvm/svm/svm.c        Thu Mar 08 09:17:21 2012 +0000
@@ -1505,6 +1505,18 @@
         if ( rdmsr_safe(msr, *msr_content) == 0 )
             break;
 
+        if ( msr == MSR_F10_BU_CFG )
+        {
+            /* Win2k8 x64 reads this MSR on revF chips, where it
+             * wasn't publically available; it uses a magic constant
+             * in %rdi as a password, which we don't have in
+             * rdmsr_safe().  Since we'll ignore the later writes,
+             * just use a plausible value here (the reset value from
+             * rev10h chips) if the real CPU didn't provide one. */
+            *msr_content = 0x0000000010200020ull;
+            break;
+        }
+
         goto gpf;
     }
 
diff -r 02216ba702b0 -r 322300fd2ebd xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h   Thu Mar 08 09:16:09 2012 +0000
+++ b/xen/include/asm-x86/msr-index.h   Thu Mar 08 09:17:21 2012 +0000
@@ -209,6 +209,9 @@
 #define MSR_F10_MC4_MISC2              0xc0000409
 #define MSR_F10_MC4_MISC3              0xc000040A
 
+/* AMD Family10h MMU control MSRs */
+#define MSR_F10_BU_CFG                  0xc0011023
+
 /* Other AMD Fam10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058
 #define FAM10H_MMIO_CONF_ENABLE         (1<<0)

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