[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [UNIKRAFT PATCH] arch: Define the cache line size for each architecture
This definition statically describes the d-cache line size in bytes for {x86_64,arm,arm64}. The d-cache line is a L1 data cache nearest to the processor and the line size refers to the data memory block. The d-line cache size can also be discovered by querying the d-cache build egister at the expense of using more memory and instruction cycles during boot. Defining this size statically increases performance since it is already known for the respective architecture. Signed-off-by: Alexander Jung <alexander.jung@xxxxxxxxx> --- arch/arm/arm/include/uk/asm/lcpu.h | 2 ++ arch/arm/arm64/include/uk/asm/lcpu.h | 2 ++ arch/x86/x86_64/include/uk/asm/lcpu.h | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch/arm/arm/include/uk/asm/lcpu.h b/arch/arm/arm/include/uk/asm/lcpu.h index cdeffc3..33f3a6b 100644 --- a/arch/arm/arm/include/uk/asm/lcpu.h +++ b/arch/arm/arm/include/uk/asm/lcpu.h @@ -29,6 +29,8 @@ #error Do not include this header directly #endif +#define CACHE_LINE_SIZE 32 + struct __regs { unsigned long r0; unsigned long r1; diff --git a/arch/arm/arm64/include/uk/asm/lcpu.h b/arch/arm/arm64/include/uk/asm/lcpu.h index 45d1b23..4597e40 100644 --- a/arch/arm/arm64/include/uk/asm/lcpu.h +++ b/arch/arm/arm64/include/uk/asm/lcpu.h @@ -30,6 +30,8 @@ #error Do not include this header directly #endif +#define CACHE_LINE_SIZE 64 + #ifdef __ASSEMBLY__ /* * Stack size to save general purpose registers and essential system diff --git a/arch/x86/x86_64/include/uk/asm/lcpu.h b/arch/x86/x86_64/include/uk/asm/lcpu.h index 6a471a1..ff137f8 100644 --- a/arch/x86/x86_64/include/uk/asm/lcpu.h +++ b/arch/x86/x86_64/include/uk/asm/lcpu.h @@ -32,6 +32,8 @@ #error Do not include this header directly #endif +#define CACHE_LINE_SIZE 64 + #ifndef __ASSEMBLY__ struct __regs { unsigned long pad; /* 8 bytes to make struct size multiple of 16 */ -- 2.11.0
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