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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Minios-devel] [UNIKRAFT/PLAT_RASPI PATCH 07/13] plats/raspi: Adding interrupt handling
Adding interrupt handling. Signed-off-by: Santiago Pagani <santiagopagani@xxxxxxxxx> --- entry.S | 314 ++++++++++++++++++++++++++++++++++++++++++ include/raspi/entry.h | 114 +++++++++++++++ include/raspi/irq.h | 68 +++++++++ irq.c | 117 ++++++++++++++++ irq_asm.S | 42 ++++++ 5 files changed, 655 insertions(+) create mode 100644 entry.S create mode 100644 include/raspi/entry.h create mode 100644 include/raspi/irq.h create mode 100644 irq.c create mode 100644 irq_asm.S diff --git a/entry.S b/entry.S new file mode 100644 index 0000000..4b7ff6c --- /dev/null +++ b/entry.S @@ -0,0 +1,314 @@ +/* + * MIT License + * + * Copyright (c) 2018, Sergey Matyukevich + * (c) 2020, Santiago Pagani <santiagopagani@xxxxxxxxx> + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +#include <raspi/entry.h> + + .macro handle_invalid_entry type + kernel_entry + mov x0, #\type + bl show_invalid_entry_message + b err_hang + .endm + + .macro ventry label + .align 7 + b \label + .endm + + .macro kernel_entry + sub sp, sp, #S_FRAME_SIZE + stp x0, x1, [sp, #16 * 0] + stp x2, x3, [sp, #16 * 1] + stp x4, x5, [sp, #16 * 2] + stp x6, x7, [sp, #16 * 3] + stp x8, x9, [sp, #16 * 4] + stp x10, x11, [sp, #16 * 5] + stp x12, x13, [sp, #16 * 6] + stp x14, x15, [sp, #16 * 7] + stp x16, x17, [sp, #16 * 8] + stp x18, x19, [sp, #16 * 9] + stp x20, x21, [sp, #16 * 10] + stp x22, x23, [sp, #16 * 11] + stp x24, x25, [sp, #16 * 12] + stp x26, x27, [sp, #16 * 13] + stp x28, x29, [sp, #16 * 14] + str x30, [sp, #16 * 15] + .endm + + .macro kernel_exit + ldp x0, x1, [sp, #16 * 0] + ldp x2, x3, [sp, #16 * 1] + ldp x4, x5, [sp, #16 * 2] + ldp x6, x7, [sp, #16 * 3] + ldp x8, x9, [sp, #16 * 4] + ldp x10, x11, [sp, #16 * 5] + ldp x12, x13, [sp, #16 * 6] + ldp x14, x15, [sp, #16 * 7] + ldp x16, x17, [sp, #16 * 8] + ldp x18, x19, [sp, #16 * 9] + ldp x20, x21, [sp, #16 * 10] + ldp x22, x23, [sp, #16 * 11] + ldp x24, x25, [sp, #16 * 12] + ldp x26, x27, [sp, #16 * 13] + ldp x28, x29, [sp, #16 * 14] + ldr x30, [sp, #16 * 15] + add sp, sp, #S_FRAME_SIZE + eret + .endm + + +/* + * Exception vectors. + */ +.align 11 +.globl vectors_el3 +vectors_el3: + ventry sync_invalid_el3t // Synchronous EL3t + ventry irq_invalid_el3t // IRQ EL3t + ventry fiq_invalid_el3t // FIQ EL3t + ventry error_invalid_el3t // Error EL3t + + ventry sync_invalid_el3h // Synchronous EL3h + ventry irq_invalid_el3h // IRQ EL3h + ventry fiq_invalid_el3h // FIQ EL3h + ventry error_invalid_el3h // Error EL3h + + ventry sync_invalid_el2_64 // Synchronous 64-bit EL2 + ventry irq_invalid_el2_64 // IRQ 64-bit EL2 + ventry fiq_invalid_el2_64 // FIQ 64-bit EL2 + ventry error_invalid_el2_64 // Error 64-bit EL2 + + ventry sync_invalid_el2_32 // Synchronous 32-bit EL2 + ventry irq_invalid_el2_32 // IRQ 32-bit EL2 + ventry fiq_invalid_el2_32 // FIQ 32-bit EL2 + ventry error_invalid_el2_32 // Error 32-bit EL2 + +.align 11 +.globl vectors_el2 +vectors_el2: + ventry sync_invalid_el2t // Synchronous EL2t + ventry irq_invalid_el2t // IRQ EL2t + ventry fiq_invalid_el2t // FIQ EL2t + ventry error_invalid_el2t // Error EL2t + + ventry sync_invalid_el2h // Synchronous EL2h + ventry irq_invalid_el2h // IRQ EL2h + ventry fiq_invalid_el2h // FIQ EL2h + ventry error_invalid_el2h // Error EL2h + + ventry sync_invalid_el1_64 // Synchronous 64-bit EL1 + ventry irq_invalid_el1_64 // IRQ 64-bit EL1 + ventry fiq_invalid_el1_64 // FIQ 64-bit EL1 + ventry error_invalid_el1_64 // Error 64-bit EL1 + + ventry sync_invalid_el1_32 // Synchronous 32-bit EL1 + ventry irq_invalid_el1_32 // IRQ 32-bit EL1 + ventry fiq_invalid_el1_32 // FIQ 32-bit EL1 + ventry error_invalid_el1_32 // Error 32-bit EL1 + +.align 11 +.globl vectors_el1 +vectors_el1: + ventry sync_invalid_el1t // Synchronous EL1t + ventry irq_invalid_el1t // IRQ EL1t + ventry fiq_invalid_el1t // FIQ EL1t + ventry error_invalid_el1t // Error EL1t + + ventry el1_sync // Synchronous EL1h + ventry el1_irq // IRQ EL1h + ventry fiq_invalid_el1h // FIQ EL1h + ventry error_invalid_el1h // Error EL1h + + ventry sync_invalid_el0_64 // Synchronous 64-bit EL0 + ventry irq_invalid_el0_64 // IRQ 64-bit EL0 + ventry fiq_invalid_el0_64 // FIQ 64-bit EL0 + ventry error_invalid_el0_64 // Error 64-bit EL0 + + ventry sync_invalid_el0_32 // Synchronous 32-bit EL0 + ventry irq_invalid_el0_32 // IRQ 32-bit EL0 + ventry fiq_invalid_el0_32 // FIQ 32-bit EL0 + ventry error_invalid_el0_32 // Error 32-bit EL0 + +sync_invalid_el3t: + handle_invalid_entry SYNC_INVALID_EL3t + +irq_invalid_el3t: + handle_invalid_entry IRQ_INVALID_EL3t + +fiq_invalid_el3t: + handle_invalid_entry FIQ_INVALID_EL3t + +error_invalid_el3t: + handle_invalid_entry ERROR_INVALID_EL3t + +sync_invalid_el3h: + handle_invalid_entry SYNC_INVALID_EL3h + +irq_invalid_el3h: + handle_invalid_entry IRQ_INVALID_EL3h + +fiq_invalid_el3h: + handle_invalid_entry FIQ_INVALID_EL3h + +error_invalid_el3h: + handle_invalid_entry ERROR_INVALID_EL3h + +sync_invalid_el2_64: + handle_invalid_entry SYNC_INVALID_EL2_64 + +irq_invalid_el2_64: + handle_invalid_entry IRQ_INVALID_EL2_64 + +fiq_invalid_el2_64: + handle_invalid_entry FIQ_INVALID_EL2_64 + +error_invalid_el2_64: + handle_invalid_entry ERROR_INVALID_EL2_64 + +sync_invalid_el2_32: + handle_invalid_entry SYNC_INVALID_EL2_32 + +irq_invalid_el2_32: + handle_invalid_entry IRQ_INVALID_EL2_32 + +fiq_invalid_el2_32: + handle_invalid_entry FIQ_INVALID_EL2_32 + +error_invalid_el2_32: + handle_invalid_entry ERROR_INVALID_EL2_32 + +sync_invalid_el2t: + handle_invalid_entry SYNC_INVALID_EL2t + +irq_invalid_el2t: + handle_invalid_entry IRQ_INVALID_EL2t + +fiq_invalid_el2t: + handle_invalid_entry FIQ_INVALID_EL2t + +error_invalid_el2t: + handle_invalid_entry ERROR_INVALID_EL2t + +sync_invalid_el2h: + handle_invalid_entry SYNC_INVALID_EL2h + +irq_invalid_el2h: + handle_invalid_entry IRQ_INVALID_EL2h + +fiq_invalid_el2h: + handle_invalid_entry FIQ_INVALID_EL2h + +error_invalid_el2h: + handle_invalid_entry ERROR_INVALID_EL2h + +sync_invalid_el1_64: + handle_invalid_entry SYNC_INVALID_EL1_64 + +irq_invalid_el1_64: + handle_invalid_entry IRQ_INVALID_EL1_64 + +fiq_invalid_el1_64: + handle_invalid_entry FIQ_INVALID_EL1_64 + +error_invalid_el1_64: + handle_invalid_entry ERROR_INVALID_EL1_64 + +sync_invalid_el1_32: + handle_invalid_entry SYNC_INVALID_EL1_32 + +irq_invalid_el1_32: + handle_invalid_entry IRQ_INVALID_EL1_32 + +fiq_invalid_el1_32: + handle_invalid_entry FIQ_INVALID_EL1_32 + +error_invalid_el1_32: + handle_invalid_entry ERROR_INVALID_EL1_32 + +sync_invalid_el1t: + handle_invalid_entry SYNC_INVALID_EL1t + +irq_invalid_el1t: + handle_invalid_entry IRQ_INVALID_EL1t + +fiq_invalid_el1t: + handle_invalid_entry FIQ_INVALID_EL1t + +error_invalid_el1t: + handle_invalid_entry ERROR_INVALID_EL1t + +sync_invalid_el1h: + handle_invalid_entry SYNC_INVALID_EL1h + +irq_invalid_el1h: + handle_invalid_entry IRQ_INVALID_EL1h + +fiq_invalid_el1h: + handle_invalid_entry FIQ_INVALID_EL1h + +error_invalid_el1h: + handle_invalid_entry ERROR_INVALID_EL1h + +sync_invalid_el0_64: + handle_invalid_entry SYNC_INVALID_EL0_64 + +irq_invalid_el0_64: + handle_invalid_entry IRQ_INVALID_EL0_64 + +fiq_invalid_el0_64: + handle_invalid_entry FIQ_INVALID_EL0_64 + +error_invalid_el0_64: + handle_invalid_entry ERROR_INVALID_EL0_64 + +sync_invalid_el0_32: + handle_invalid_entry SYNC_INVALID_EL0_32 + +irq_invalid_el0_32: + handle_invalid_entry IRQ_INVALID_EL0_32 + +fiq_invalid_el0_32: + handle_invalid_entry FIQ_INVALID_EL0_32 + +error_invalid_el0_32: + handle_invalid_entry ERROR_INVALID_EL0_32 + +el1_sync: + kernel_entry + mrs x0, ESR_EL1 + mrs x1, FAR_EL1 + bl show_invalid_entry_message_el1_sync + b err_hang + +el1_irq: + kernel_entry + bl ukplat_irq_handle + kernel_exit + +.globl err_hang +err_hang: b err_hang diff --git a/include/raspi/entry.h b/include/raspi/entry.h new file mode 100644 index 0000000..2b116f0 --- /dev/null +++ b/include/raspi/entry.h @@ -0,0 +1,114 @@ +/* + * MIT License + * + * Copyright (c) 2018, Sergey Matyukevich <https://github.com/s-matyukevich/raspberry-pi-os> + * (c) 2020, Santiago Pagani <santiagopagani@xxxxxxxxx> + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RASPI_ENTRY_H__ +#define __RASPI_ENTRY_H__ + +#define S_FRAME_SIZE 256 // Size of all saved registers + +#define SYNC_INVALID_EL3t 0 +#define IRQ_INVALID_EL3t 1 +#define FIQ_INVALID_EL3t 2 +#define ERROR_INVALID_EL3t 3 + +#define SYNC_INVALID_EL3h 4 +#define IRQ_INVALID_EL3h 5 +#define FIQ_INVALID_EL3h 6 +#define ERROR_INVALID_EL3h 7 + +#define SYNC_INVALID_EL2_64 8 +#define IRQ_INVALID_EL2_64 9 +#define FIQ_INVALID_EL2_64 10 +#define ERROR_INVALID_EL2_64 11 + +#define SYNC_INVALID_EL2_32 12 +#define IRQ_INVALID_EL2_32 13 +#define FIQ_INVALID_EL2_32 14 +#define ERROR_INVALID_EL2_32 15 + +#define SYNC_INVALID_EL2t 16 +#define IRQ_INVALID_EL2t 17 +#define FIQ_INVALID_EL2t 18 +#define ERROR_INVALID_EL2t 19 + +#define SYNC_INVALID_EL2h 20 +#define IRQ_INVALID_EL2h 21 +#define FIQ_INVALID_EL2h 22 +#define ERROR_INVALID_EL2h 23 + +#define SYNC_INVALID_EL1_64 24 +#define IRQ_INVALID_EL1_64 25 +#define FIQ_INVALID_EL1_64 26 +#define ERROR_INVALID_EL1_64 27 + +#define SYNC_INVALID_EL1_32 28 +#define IRQ_INVALID_EL1_32 29 +#define FIQ_INVALID_EL1_32 30 +#define ERROR_INVALID_EL1_32 31 + +#define SYNC_INVALID_EL1t 32 +#define IRQ_INVALID_EL1t 33 +#define FIQ_INVALID_EL1t 34 +#define ERROR_INVALID_EL1t 35 + +#define SYNC_INVALID_EL1h 36 +#define IRQ_INVALID_EL1h 37 +#define FIQ_INVALID_EL1h 38 +#define ERROR_INVALID_EL1h 49 + +#define SYNC_INVALID_EL0_64 40 +#define IRQ_INVALID_EL0_64 41 +#define FIQ_INVALID_EL0_64 42 +#define ERROR_INVALID_EL0_64 43 + +#define SYNC_INVALID_EL0_32 44 +#define IRQ_INVALID_EL0_32 45 +#define FIQ_INVALID_EL0_32 46 +#define ERROR_INVALID_EL0_32 47 + +#define SYNC_INVALID_EL0t 48 +#define IRQ_INVALID_EL0t 49 +#define FIQ_INVALID_EL0t 50 +#define ERROR_INVALID_EL0t 51 + +#define SYNC_INVALID_EL0h 52 +#define IRQ_INVALID_EL0h 53 +#define FIQ_INVALID_EL0h 54 +#define ERROR_INVALID_EL0h 55 + +#define SYNC_INVALID_ELN_64 56 +#define IRQ_INVALID_ELN_64 57 +#define FIQ_INVALID_ELN_64 58 +#define ERROR_INVALID_ELN_64 59 + +#define SYNC_INVALID_ELN_32 60 +#define IRQ_INVALID_ELN_32 61 +#define FIQ_INVALID_ELN_32 62 +#define ERROR_INVALID_ELN_32 63 + +#endif /* __RASPI_ENTRY_H__ */ diff --git a/include/raspi/irq.h b/include/raspi/irq.h new file mode 100644 index 0000000..034dd98 --- /dev/null +++ b/include/raspi/irq.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Authors: Santiago Pagani <santiagopagani@xxxxxxxxx> + * + * Copyright (c) 2020, NEC Laboratories Europe GmbH, NEC Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * THIS HEADER MAY NOT BE EXTRACTED OR MODIFIED IN ANY WAY. + */ + +#ifndef __RASPI_IRQ_H__ +#define __RASPI_IRQ_H__ + +#include <raspi/sysregs.h> + +#define IRQ_BASIC_PENDING ((volatile __u32 *)(MMIO_BASE+0x0000B200)) +#define IRQ_PENDING_1 ((volatile __u32 *)(MMIO_BASE+0x0000B204)) +#define IRQ_PENDING_2 ((volatile __u32 *)(MMIO_BASE+0x0000B208)) +#define FIQ_CONTROL ((volatile __u32 *)(MMIO_BASE+0x0000B20C)) +#define ENABLE_IRQS_1 ((volatile __u32 *)(MMIO_BASE+0x0000B210)) +#define ENABLE_IRQS_2 ((volatile __u32 *)(MMIO_BASE+0x0000B214)) +#define ENABLE_BASIC_IRQS ((volatile __u32 *)(MMIO_BASE+0x0000B218)) +#define DISABLE_IRQS_1 ((volatile __u32 *)(MMIO_BASE+0x0000B21C)) +#define DISABLE_IRQS_2 ((volatile __u32 *)(MMIO_BASE+0x0000B220)) +#define DISABLE_BASIC_IRQS ((volatile __u32 *)(MMIO_BASE+0x0000B224)) + +#define IRQS_BASIC_ARM_TIMER_IRQ (1 << 0) + +#define IRQS_1_SYSTEM_TIMER_IRQ_0 (1 << 0) +#define IRQS_1_SYSTEM_TIMER_IRQ_1 (1 << 1) +#define IRQS_1_SYSTEM_TIMER_IRQ_2 (1 << 2) +#define IRQS_1_SYSTEM_TIMER_IRQ_3 (1 << 3) +#define IRQS_1_USB_IRQ (1 << 9) + +#define IRQS_MAX 2 +#define IRQ_ID_ARM_GENERIC_TIMER 0 +#define IRQ_ID_RASPI_ARM_SIDE_TIMER 1 + +void irq_vector_init( void ); +void enable_irq( void ); +void disable_irq( void ); + +#endif /* __RASPI_IRQ_H__ */ \ No newline at end of file diff --git a/irq.c b/irq.c new file mode 100644 index 0000000..dc13edc --- /dev/null +++ b/irq.c @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Authors: Santiago Pagani <santiagopagani@xxxxxxxxx> + * + * Copyright (c) 2020, NEC Laboratories Europe GmbH, NEC Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * THIS HEADER MAY NOT BE EXTRACTED OR MODIFIED IN ANY WAY. + */ + +#include <stdlib.h> +#include <uk/plat/irq.h> +#include <uk/print.h> +#include <uk/essentials.h> +#include <raspi/irq.h> +#include <raspi/time.h> +#include <raspi/raspi_info.h> +#include <arm/time.h> + +static irq_handler_func_t irq_handlers[IRQS_MAX]; + +int ukplat_irq_register(unsigned long irq, irq_handler_func_t func, void *arg __unused) +{ + switch (irq) { + case IRQ_ID_ARM_GENERIC_TIMER: + break; + case IRQ_ID_RASPI_ARM_SIDE_TIMER: + *ENABLE_BASIC_IRQS = *ENABLE_BASIC_IRQS | IRQS_BASIC_ARM_TIMER_IRQ; + raspi_arm_side_timer_irq_clear(); + raspi_arm_side_timer_irq_enable(); + break; + default: + // Unsupported IRQ + uk_pr_crit("ukplat_irq_register: Unsupported IRQ\n"); + return -1; + } + + irq_handlers[irq] = func; + return 0; +} + +int ukplat_irq_init(struct uk_alloc *a __unused) +{ + for (unsigned int i = 0; i < IRQS_MAX; i++) { + irq_handlers[i] = NULL; + } + *DISABLE_BASIC_IRQS = 0xFFFFFFFF; + *DISABLE_IRQS_1 = 0xFFFFFFFF; + *DISABLE_IRQS_2 = 0xFFFFFFFF; + irq_vector_init(); + enable_irq(); + return 0; +} + +void show_invalid_entry_message(int type) +{ + uk_pr_debug("IRQ: %d\n", type); +} + +void show_invalid_entry_message_el1_sync(uint64_t esr_el, uint64_t far_el) +{ + uk_pr_debug("ESR_EL1: %lx, FAR_EL1: %lx, SCTLR_EL1:%lx\n", esr_el, far_el, get_sctlr_el1()); +} + +void ukplat_irq_handle(void) +{ + __u32 irq_bits = *IRQ_BASIC_PENDING & *ENABLE_BASIC_IRQS; + if ((irq_bits & IRQS_BASIC_ARM_TIMER_IRQ) && irq_handlers[IRQ_ID_RASPI_ARM_SIDE_TIMER]) { + irq_handlers[IRQ_ID_RASPI_ARM_SIDE_TIMER](NULL); + return; + } + + if ((get_el0(cntv_ctl) & GT_TIMER_IRQ_STATUS) && irq_handlers[IRQ_ID_ARM_GENERIC_TIMER]) { + irq_handlers[IRQ_ID_ARM_GENERIC_TIMER](NULL); + return; + } + + uk_pr_crit("ukplat_irq_handle: Unhandled IRQ\n"); + uk_pr_crit("IRQ_BASIC_PENDING: %u\n", *IRQ_BASIC_PENDING); + uk_pr_crit("IRQ_PENDING_1: %u\n", *IRQ_PENDING_1); + uk_pr_crit("IRQ_PENDING_2: %u\n", *IRQ_PENDING_2); + uk_pr_crit("ENABLE_BASIC_IRQS: %u\n", *ENABLE_BASIC_IRQS); + uk_pr_crit("ENABLE_IRQS_1: %u\n", *ENABLE_IRQS_1); + uk_pr_crit("ENABLE_IRQS_2: %u\n", *ENABLE_IRQS_2); + uk_pr_crit("DISABLE_BASIC_IRQS: %u\n", *DISABLE_BASIC_IRQS); + uk_pr_crit("DISABLE_IRQS_1: %u\n", *DISABLE_IRQS_1); + uk_pr_crit("DISABLE_IRQS_2: %u\n", *DISABLE_IRQS_2); + uk_pr_crit("get_el0(cntv_ctl): %lu\n", get_el0(cntv_ctl)); + uk_pr_crit("irq_handlers[IRQ_ID_ARM_GENERIC_TIMER]: %lu\n", (unsigned long)irq_handlers[IRQ_ID_ARM_GENERIC_TIMER]); + uk_pr_crit("irq_handlers[IRQ_ID_RASPI_ARM_SIDE_TIMER]: %lu\n", (unsigned long)irq_handlers[IRQ_ID_RASPI_ARM_SIDE_TIMER]); + while(1); +} diff --git a/irq_asm.S b/irq_asm.S new file mode 100644 index 0000000..0058d23 --- /dev/null +++ b/irq_asm.S @@ -0,0 +1,42 @@ +/* + * MIT License + * + * Copyright (c) 2018, Sergey Matyukevich <https://github.com/s-matyukevich/raspberry-pi-os> + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +.globl irq_vector_init +irq_vector_init: + adr x0, vectors_el1 // load VBAR_EL1 with virtual + msr vbar_el1, x0 // vector table address + ret + +.globl enable_irq +enable_irq: + msr daifclr, #2 + ret + +.globl disable_irq +disable_irq: + msr daifset, #2 + ret -- 2.17.1 _______________________________________________ Minios-devel mailing list Minios-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/minios-devel
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