Re: [Minios-devel] [UNIKRAFT PATCHv5 3/6] plat/common: Implement gic-v2 library for Arm

[Julien Grall <julien.grall@xxxxxxx>]

Hi,

On 6/28/19 8:09 AM, Jia He wrote:
> +static void gic_init_dist(void)
> +{
> +       uint32_t val, cpuif_number, irq_number;
> +       uint32_t i;
> +
> +       /* Turn down distributor */
> +       gic_disable_dist();
> +
> +       /* Get GIC CPU interface */
> +       val = read_gicd32(GICD_TYPER);
> +       cpuif_number = GICD_TYPER_CPUI_NUM(val);
> +       if (cpuif_number > GIC_MAX_CPUIF)
> +               cpuif_number = GIC_MAX_CPUIF;
> +       uk_pr_info("GICv2 Max CPU interface:%d\n", cpuif_number);
> +
> +       /* Get the maximum number of interrupts that the GIC supports */
> +       irq_number = GICD_TYPER_LINE_NUM(val);
> +       if (irq_number > GIC_MAX_IRQ)
> +               irq_number = GIC_MAX_IRQ;
> +       uk_pr_info("GICv2 Max interrupt lines:%d\n", irq_number);
> +       /*
> +        * Set all SPI interrupts targets to all CPU.
> +        */
> +       for (i = GIC_SPI_BASE; i < irq_number; i += GICD_I_PER_ITARGETSRn)
> +               write_gicd32(GICD_ITARGETSR(i), GICD_ITARGETSR_DEF);
> +
> +       /*
> +        * Set all SPI interrupts type to be level triggered
> +        */
> +       for (i = GIC_SPI_BASE; i < irq_number; i += GICD_I_PER_ICFGRn)
> +               write_gicd32(GICD_ICFGR(i), GICD_ICFGR_DEF_TYPE);
Why do you initialize SPI interrupts type to level-triggered? What if 
they are edge?
> +
> +       /*
> +        * Set all SPI priority to a default value.
> +        */
> +       for (i = GIC_SPI_BASE; i < irq_number; i += GICD_I_PER_IPRIORITYn)
> +               write_gicd32(GICD_IPRIORITYR(i), GICD_IPRIORITY_DEF);
> +
> +       /*
> +        * Deactivate and disable all SPIs.
> +        */
> +       for (i = GIC_SPI_BASE; i < irq_number; i += GICD_I_PER_ICACTIVERn) {
> +               write_gicd32(GICD_ICACTIVER(i), GICD_DEF_ICACTIVERn);
> +               write_gicd32(GICD_ICENABLER(i), GICD_DEF_ICENABLERn);
> +       }
> +
> +       /* turn on distributor */
> +       gic_enable_dist();
> +}
> +
> +static void gic_init_cpuif(void)
> +{
> +       uint32_t i;
> +       /*
> +        * set priority mask to the lowest priority to let all irq
> +        * visible to cpu interface
> +        */
> +       gic_set_threshold_priority(GICC_PMR_PRIO_MAX);
> +
> +       /* set PPI and SGI to level triggered */
> +       for (i = 0; i < GIC_SPI_BASE; i += GICD_I_PER_ICFGRn)
> +               write_gicd32(GICD_ICFGR(i), GICD_ICFGR_DEF_TYPE);
Ditto.

Cheers,

--
Julien Grall

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