[Minios-devel] [UNIKRAFT PATCH 2/5] arch/arm64: Define the size of callee-saved-registers for thread switch

[Wei Chen <wei.chen@xxxxxxx>]

In thread context switch, we will save the callee-saved registers
(x19 ~ x28) and Frame Point Register and Link Register to prev's
thread stack:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/ch09s01s01.html

Signed-off-by: Wei Chen <wei.chen@xxxxxxx>
Signed-off-by: Jianyong Wu <jianyong.wu@xxxxxxx>
---
 arch/arm/arm64/include/uk/asm/lcpu.h | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/arm64/include/uk/asm/lcpu.h 
b/arch/arm/arm64/include/uk/asm/lcpu.h
index 6138d3b..6536e4f 100644
--- a/arch/arm/arm64/include/uk/asm/lcpu.h
+++ b/arch/arm/arm64/include/uk/asm/lcpu.h
@@ -44,6 +44,15 @@
 #define __TRAP_STACK_SIZE      288
 #define __SP_OFFSET            272
 #define __SP_EL0_OFFSET                280
+
+/*
+ * In thread context switch, we will save the callee-saved registers
+ * (x19 ~ x28) and Frame Point Register and Link Register to prev's
+ * thread stack:
+ * 
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/ch09s01s01.html
+ */
+#define __CALLEE_SAVED_SIZE    96
+
 #else
 /*
  * Change this structure must update TRAP_STACK_SIZE at the same time.
@@ -72,6 +81,21 @@ struct __regs {
        unsigned long sp_el0;
 };
 
+/*
+ * Change this structure must update __CALLEE_SAVED_SIZE at the
+ * same time.
+ */
+struct __callee_saved_regs {
+       /* Callee-saved registers, from x19 ~ x28 */
+       unsigned long callee[10];
+
+       /* Frame Point Register (x29) */
+       unsigned long fp;
+
+       /* Link Register (x30) */
+       unsigned long lr;
+};
+
 /*
  * Instruction Synchronization Barrier flushes the pipeline in the
  * processor, so that all instructions following the ISB are fetched
-- 
2.17.1


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