Re: [Minios-devel] [UNIKRAFT PATCHv4 22/43] plat/kvm: Allow access to floating-point and Advanced SIMD registers

[Wei Chen <Wei.Chen@xxxxxxx>]

Hi, Julien,

> -----Original Message-----
> From: Julien Grall <julien.grall@xxxxxxx>
> Sent: 2018年7月8日 6:17
> To: Wei Chen <Wei.Chen@xxxxxxx>; minios-devel@xxxxxxxxxxxxxxxxxxxx;
> simon.kuenzer@xxxxxxxxx
> Cc: Kaly Xin <Kaly.Xin@xxxxxxx>; nd <nd@xxxxxxx>
> Subject: Re: [Minios-devel] [UNIKRAFT PATCHv4 22/43] plat/kvm: Allow access to
> floating-point and Advanced SIMD registers
> 
> Hi,
> 
> On 07/06/2018 10:03 AM, Wei Chen wrote:
> > On Arm64, when we want to print out some message, the va_list will
> > use the SIMD&FP registers (like q0, q1) to store parameters. So, we
> > have to disable the trap of accessing floating-point and Advanced SIMD
> > registers to make va_list use SIMD&FP registers properly.
> 
> I don't think this is true. Xen and Linux don't use SIMD&FP registers as
> this would require to context switch at every entry. Yet we are able to
> use va_list without SIMD&FP registers.
> 

This is true, because Linux and Xen doesn't support float print.
Unikraft kernel just a part of an application, its print library need
To support float. Just like nolibc, when GCC compiling this library,
it doesn't care you are running EL1 or EL0, the generated code will
access q0, q1. When you're running this code in EL1 without SIMD&FP,
system crash.

> Cheers,
> 
> >
> > Signed-off-by: Wei Chen <Wei.Chen@xxxxxxx>
> > ---
> >   plat/common/include/arm/arm64/cpu_defs.h | 12 ++++++++++++
> >   plat/kvm/arm/entry64.S                   | 10 ++++++++++
> >   2 files changed, 22 insertions(+)
> >
> > diff --git a/plat/common/include/arm/arm64/cpu_defs.h
> b/plat/common/include/arm/arm64/cpu_defs.h
> > index b7eba93..6bbd142 100644
> > --- a/plat/common/include/arm/arm64/cpu_defs.h
> > +++ b/plat/common/include/arm/arm64/cpu_defs.h
> > @@ -76,6 +76,18 @@ END(name)
> >
> >   #endif
> >
> > +/*
> > + * CPACR_EL1 Architectural Feature Access Control Register
> > + * FPEN, bits [21:20] control traps of EL0 and EL1 accesses to the
> > + * SIMD and floating-point registers to EL1, from both Execution
> > + * states.
> > +*/
> > +#define CPACR_FPEN_MASK         (0x3 << 20)
> > +/* Any access in EL0 or EL1 will be trapped */
> > +#define CPACR_FPEN_TRAP_ALL     (0x0 << 20)
> > +/* Any access in EL0 or EL1 will not be trapped */
> > +#define CPACR_FPEN_TRAP_NONE    (0x3 << 20)
> > +
> >   /* Define the address offset of boot stack and pagetable */
> >   #define PAGE_SIZE __PAGE_SIZE
> >   #define PAGE_SHIFT        __PAGE_SHIFT
> > diff --git a/plat/kvm/arm/entry64.S b/plat/kvm/arm/entry64.S
> > index 8a8a2e0..8b470c1 100644
> > --- a/plat/kvm/arm/entry64.S
> > +++ b/plat/kvm/arm/entry64.S
> > @@ -29,6 +29,16 @@ ENTRY(_libkvmplat_entry)
> >
> >     mov sp, x27
> >
> > +   /*
> > +    * In order to handle the va_list, the SIMD&FP registers (like q0, q1)
> > +    * would be used. So, we have to enable the floating-point and Advanced
> > +    * SIMD registers.
> > +    */
> > +   mrs x0, cpacr_el1
> > +   bic x0, x0, #(~CPACR_FPEN_MASK)
> > +   orr x0, x0, #CPACR_FPEN_TRAP_NONE
> > +   msr cpacr_el1, x0
> > +
> >
> >     /* Load dtb address to x0 as a parameter */
> >     ldr x0, =_dtb
> >
> 
> --
> Julien Grall
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