Re: [Minios-devel] [PATCH v3 28/43] arm64: init the memory system

[Julien Grall <julien.grall@xxxxxxx>]

On 28/04/18 10:37, Huang Shijie wrote:
> On Thu, Apr 26, 2018 at 02:19:52PM +0100, Julien Grall wrote:
> > On 16/04/18 07:32, Huang Shijie wrote:
> > > +void arch_mm_preinit(void *dtb_pointer)
> > > +{
> > > +    paddr_t **dtb_p = dtb_pointer;
> > > +    paddr_t *dtb = *dtb_p;
> > > +    uintptr_t end = (uintptr_t) &_end;
> > > +
> > > +    dtb = to_virt(((paddr_t)dtb));
> > > +    first_free_pfn = PFN_UP(to_phys(end));
> > > +    min_mem_pfn = PFN_UP(to_phys(_text) + MIN_MEM_SIZE);
> > > +
> > > +    /*
> > > +     * Setup the mapping for Device Tree, only map 2M(L2_SIZE) size.
> > > +     *
> > > +     * Note: The early_alloc_page() will increase @first_free_pfn.
> > > +     */
> > > +    build_pagetable((unsigned long)dtb, virt_to_pfn((unsigned long)dtb),
> > > +                    PHYS_PFN(L2_SIZE), MEM_DEF_ATTR, early_alloc_page, 2);
> > I forgot to comment on this. You can't assume the DTB will be 2MB aligned
> Is there any document about this?
Yes, the one describing the booting protocol for booting Linux Image 
format (see linux/Documentation/arm64/booting.txt).
> I thought the DTB is 2M aligned.
"The device tree blob (dtb) must be placed on an 8-byte boundary and 
must not exceed 2 megabytes in size. Since the dtb will be mapped 
cacheable using blocks of up to 2 megabytes in size, it must not be 
placed within any 2M region which must be mapped with any specific 
attributes."
> > and the interface of build_pagetable is somewhat quite confusing to use. So
> > are you going to map 2 2MB section? Or only one?
> What's the "section" mean? do you mean one PMD entry.
>
> The code only maps one PMD entry.
I still have no clue what you mean by PMD. What I meant by section is 
block mapping (to use the Arm Arm term). It is allowed to do mapping at 
L1 and L2. For 4KB, they would resp. be 1GB and 2MB.
Cheers.

--
Julien Grall

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