[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH] Improve the current FLR logic
Yuji, Could you show me how to use the hotplug method to restore the register? Also, in the current implementation, we just read 4 bytes each time and write them from 0 to 256 - 4. Will this cause any side effect? Thanks, Neo On Thu, Jul 17, 2008 at 2:33 AM, Yuji Shimada <shimada-yxb@xxxxxxxxxxxxxxx> wrote: > On Sat, 12 Jul 2008 20:37:34 +0800 > "Cui, Dexuan" <dexuan.cui@xxxxxxxxx> wrote: > >> I'd like to ask for your comments, and test feedbacks. Thank you very >> much! > > There is a problem with the device reconfiguring logic. xend saves all > Configuration Register's values before reset. And xend writes the > values to the registers after reset. This means the resister's values > which are configured by guest software are restore. Guest software > setting should be cleared. > > I think the following Configuration Resister should be reconfigured to > correct values after reset. And other registers should not be > reconfigured after reset if there is no reason. > > - It is necessary to write the base address of the resource allocated > by the dom0 kernel to the following resister. > - Base Address Register > > - When dom0 starts, the values configured by firmware should be saved, > and the values should be written to the following resisters after > reset. The reason is that firmware configures them to archive system > specific functions. Especially, the registers relating error reporting > are configured to collect error information. If this configured values > is changed, some functions might be lost. > Instead of save/restore, it is good way to write the value from _HPX > method to registers, I think. _HPX method returns the value to write > to registers. > - Cache-line size Register > - Latency timer Register > - Enable SERR Bit/Enable PERR Bit in Device Control Register > - Uncorrectable Error Mask Register > - Uncorrectable Error Severity Register > - Correctable Error Mask Register > - Advanced Error Capabilities and Control Register > - Device Control Register > - Link Control Register > - Secondary Uncorrectable Error Severity Register > - Secondary Uncorrectable Error Mask Register > - Device Control 2 Register > - Link Control 2 Register > > - The following resister should be configured to "0". > - PME Enable Bit/PME Status Bit in PCI Power Management > Control/Status Register > > I would like to discuss this logic more. > > Thanks. > > -- > Yuji Shimada > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@xxxxxxxxxxxxxxxxxxx > http://lists.xensource.com/xen-devel > -- I would remember that if researchers were not ambitious probably today we haven't the technology we are using! _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel
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