|
On 25/7/07 07:43, "Kaushik Barde" <Kaushik_Barde@xxxxxxxxxxx> wrote: > Thanks. > >>> > via masking of maskable interrupts > << > What I'd meant there was all other interrupts are masked (by processor during > NMI handling) except for NMI. NMIs *are* masked by x86 CPU from when an NMI is delivered to the CPU until after that CPU next executes an IRET. The CPU has a special NMI mask for this purpose (not directly architecturally visible). It's unrelated to EFLAGS.IF. -- Keir _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel
|
Copyright
, Citrix Systems Inc. All rights reserved.
Legal and Privacy
|
